HC230F1020 Altera, HC230F1020 Datasheet - Page 178

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

HardCopy Series Handbook, Volume 1
Figure 7–6. Classic Timing Analyzer Constraints Check in Compilation Report
Constraining
Timing of
HardCopy Series
Devices
7–14
The Compilation Report for both the Stratix II and HardCopy II
revisions of your project includes a Timing Constraints Check section
(Figure
coverage provided by the timing constraints used in the design. You
should examine this report and verify that all internal and I/O paths and
all clock domains are constrained for both setup and hold checks.
When using Classic Timing Analyzer, just as when using the TimeQuest
timing analyzer, you should review the Quartus II timing report sections
in the Compilation Report and resolve all reported timing violations.
To ensure that the timing of the HardCopy device meets performance
goals, the HardCopy Design Center runs static timing analysis on the
design database. For this timing analysis to be meaningful, all timing
constraints and timing exceptions that you applied to the design for the
FPGA implementation, must also be used for the HardCopy
implementation. If you did not use timing constraints or you used only
partial timing constraints for the design, you must add constraints to
7–6). This section reports all unconstrained paths based on the
Altera Corporation
September 2008