HC230F1020 Altera, HC230F1020 Datasheet - Page 145
HC230F1020
Manufacturer Part Number
HC230F1020
Description
Manufacturer
Altera
Datasheet
1.HC230F1020.pdf
(228 pages)
Specifications of HC230F1020
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HC230F1020ANQ
Manufacturer:
Discera
Quantity:
2 000
- Current page: 145 of 228
- Download datasheet (4Mb)
Making I/O
Assignments
Altera Corporation
September 2008
f
Because of the complex rules governing the use of programmable I/O
cells and their availability for specific pins and packages, Altera highly
recommends that I/O assignments are completed using the Pin Planning
tool and the Assignment Editor in the Quartus II GUI. These tools ensure
that all of the rules regarding each pin and I/O cell are applied correctly.
The Quartus II GUI can export a Tcl script containing all I/O assignments
and specifications. I/O assignments are described here for information
only.
For more information on I/O location and type assignments using the
Quartus II Assignment Editor and Pin Planner tools, refer to the
Assignment Editor chapter in volume 2 of the Quartus II Handbook.
In this section, I/O specification is considered in two parts:
■
■
Pin Assignments
Design I/O signals are assigned to package balls using the
set_location_assignment command. The syntax for this command is
given below:
tcl> set_location_assignment [-comment <comment>] \
Here, <destination> is the package ball name and <value> is the design I/O
signal name. For BGA and FBGA packages, the ball name follows the
form PIN_<coordinate>. For example, to assign design I/O signal
data_out[15] to package ball AL17:
tcl> set_location_assignment -to PIN_AL17 data_out[15]
Setting I/O Type and Parameters
For I/O type and parameter specification, the set_instance_assignment
command is used. The syntax for this command is:
tcl> set_instance_assignment [-comment <comment>] \
Pin assignments
I/O type assignments
[-disable] [-remove] -to <destination> <value>
[-disable] [-entity <entity_name>] \
[-from <source>] -name <name> [-remove] \
[-section_id <section_id>] \
[-to <destination>] <value>
Making Global Assignments
6–17
Related parts for HC230F1020
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: