HC230F1020 Altera, HC230F1020 Datasheet - Page 11

• Manufacturer Part Number: HC230F1020
• Manufacturer: Altera

Specifications of HC230F1020

• Lead Free Status / RoHS Status: Not Compliant

Figure 2–1. Example Block Diagram of HC230 Device
Note to
(1)
Altera Corporation
September 2008
Figure 2–1
Quartus II software.
Figure
2–1:
shows a graphical representation of the device floor plan. A detailed floor plan is available in the
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
IOE
of HCells
Array
Fast
PLL
Fast
PLL
IOE
M4K RAM Blocks
savings, which results in low-cost structured ASICs with
high-performance and low-power suitable for a wide variety of
applications.
The SRAM configuration cells of the Stratix II FPGAs are replaced in
HardCopy II devices with metal connections, which define the function
of logic, memory, phase-locked loop (PLL), and I/O elements (IOEs) in
the device. These resources are interconnected using metallization layers.
Once a HardCopy II device is manufactured, the functionality of the
device is fixed.
HardCopy II devices are manufactured using the same 90-nm process
technology and operate using the same core voltage (1.2 V) as Stratix II
FPGAs. Additionally, almost all architectural features in HardCopy II
devices are functionally equivalent to features found in the Stratix II
FPGA architecture. HardCopy II devices feature HCells, memory blocks,
PLLs, and IOEs
of HCells
Array
IOE
M4K RAM Blocks
(Figure
of HCells
Array
of HCells
Array
2–1).
Note (1)
IOEs
M-RAM Block
of HCells
Array
Enhanced
PLL
Functional Description
of HCells
Array
Preliminary
2–3