DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 88

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: The DLIMIT1 and DLIMIT2 registers must be read consecutively and written consecutively. See Section 8.3.
Bits 7 to 0: DPLL Hard Frequency Limit (HARDLIM[7:0]). The full 10-bit HARDLIM[9:0] field spans this register
and DLIMIT2. HARDLIM is an unsigned integer that specifies the hard frequency limit or pull-in/hold-in range of the
T0 DPLL. When frequency limit detection is enabled by setting FLLOL = 1 in the
frequency exceeds the hard limit the DPLL declares loss-of-lock. The hard frequency limit in ppm is
HARDLIM[9:0] x 0.0782. The default value is normally 9.2ppm. If external reference switching mode is enabled
during reset (see Section 7.6.5), the default value is configured to 79.794ppm (3FFh). See Section 7.7.6.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 1 to 0: DPLL Hard Frequency Limit (HARDLIM[9:8]). See the
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
—
7
0
7
0
6
1
—
6
0
DLIMIT1
DPLL Frequency Limit Register 1
41h
DLIMIT2
DPLL Frequency Limit Register 1
42h
5
1
—
5
0
—
4
1
HARDLIM[7:0]
4
0
DLIMIT1
—
3
0
3
0
register description.
—
2
1
2
0
DLIMIT3
register, if the DPLL
HARDLIM[9:8]
1
1
1
0
88 of 142
0
0
0
0