DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 38

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

7.7.13 Output Jitter and Wander
Several factors contribute to jitter and wander on the output clocks, including:
The DPLL in the device has programmable bandwidth (see Section 7.7.3). With respect to jitter and wander, the
DPLL behaves as a lowpass filter with a programmable pole. The bandwidth of the DPLL is normally set low
enough to strongly attenuate jitter. The wander and jitter attenuation depends on the DPLL bandwidth chosen.
Over time, frequency changes in the local oscillator can cause a phase difference between the selected reference
and the output clocks. This is especially true at lower frequency DPLL bandwidths because the DPLL’s rate of
change may be slower than the oscillator’s rate of change. Oscillators with better stability will minimize this effect.
In some applications, an OCXO may be required rather than a TCXO. In the most demanding applications, the
OCXO may need to be shielded to further reduce the rate of temperature change and thus the rate of frequency
change.
7.8
A total of 16 output clock pins, OC1 to OC5, OC1B to OC5B, OC4POS/NEG to OC7POS/NEG, FSYNC, and
MFSYNC are available on the device. Output clocks OC1 to OC7 are individually configurable for a variety of
frequencies derived from either the T0 DPLL or the T4 DPLL. OC1B to OC5B are powered from a dedicated I/O
power pin that can be set to any voltage from 2.2V to 3.3V. Output clocks FSYNC and MFSYNC serve as 8kHz
frame-sync and 2kHz multiframe-sync outputs, respectively.
the output clock pins.
Table 7-7. Output Clock Capabilities
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
MFSYNC
OUTPUT
CLOCK
FSYNC
OC1B
OC2B
OC3B
OC4B
OC5B
OC1
OC2
OC3
OC4
OC5
OC4
OC5
OC6
OC7



Output Clock Configuration
Jitter and wander amplitude on the selected reference (while in the locked state)
The jitter/wander transfer characteristic of the device (while in the locked state)
The jitter and wander on the local oscillator clock signal (especially wander while in the
holdover state)
LVDS/LVPECL
3.3V powered
2.5V or 3.3V
CMOS/TTL
CMOS/TTL
CMOS/TTL
FORMAT
SIGNAL
powered
Frequency selection per Section
8kHz frame sync with programmable pulse width and polarity.
2kHz multiframe sync with programmable pulse width and polarity.
FREQUENCIES SUPPORTED
Table 7-7
7.8.2.3
provides more detail on the capabilities of
and
Table 7-8
to
Table
7-14.
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