DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 34

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the
T4LOCK bit in the
7.7.7 Phase Build-Out
7.7.7.1
The T0 DPLL has a phase monitor that measures the phase error between the input clock reference and the DPLL
output. The phase monitor is enabled by setting PHMON:PMEN = 1. When the T0 DPLL is set for low bandwidth, a
phase transient on the input causes an immediate phase error that is gradually reduced as the DPLL tracks the
input. When the measured phase error exceeds the limit set in the PHMON:PMLIM field, the phase monitor
declares a phase monitor alarm by setting the MSR3:PHMON bit. The PMLIM field can be configured for a limit
ranging from about 1s to about 3.5s.
7.7.7.2
See Telcordia GR-1244-CORE Section 5.7 for an explanation of phase build-out (PBO) and the requirement for
Stratum 2 and 3E clocks to perform PBO in response to input phase transients.
When the phase monitor is enabled (as described in Section 7.7.7.1) and PHMON:PMPBEN = 1, the T0 DPLL
automatically triggers PBO events in response to input transients greater than the limit set in PHMON:PMLIM. The
range of limits available in the PMLIM field allows the T0 DPLL to be configured to build out input transients greater
than 3.5s, greater than 1s, or any threshold in between.
To determine when to perform PBO, the phase monitor watches for phase changes greater than 100ns in a 10ms
interval on the selected reference. When such a phase change occurs, an internal 0.1 second timer is started. If
during this interval the phase change is greater than the PMLIM threshold then a PBO event occurs. During a PBO
event the device enters a temporary holdover state in which the phase difference between the selected reference
and the output is measured and fed into the DPLL loop to absorb the input transient. After a PBO event, regardless
of the input phase transient, the output phase transient is less than or equal to 5ns. Phase build-out can be frozen
at the current phase offset by setting MCR10:PBOFRZ = 1. When PBO is frozen the T0 DPLL ignores subsequent
phase build-out events and maintains the current phase offset between input and outputs.
7.7.7.3 Automatic Phase Build-Out in Response to Reference Switching
When MCR10:PBOEN = 0, phase build-out is not performed during reference switching. The T0 DPLL always
locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to
the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients
on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference.
When MCR10:PBOEN = 1, phase build-out is performed during reference switching (or exiting from holdover). With
PBO enabled, if the selected reference fails and another valid reference is available, the device enters a temporary
holdover state in which the phase difference between the new reference and the output is measured and fed into
the DPLL loop to absorb the input phase difference. Similarly, during transitions from full holdover, mini-holdover,
or free-run to locked mode, the phase difference between the new reference and the output is measured and fed
into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase
difference, the output phase transient is less than or equal to 5ns.
Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ = 1.
When PBO is frozen, the T0 DPLL ignores subsequent phase build-out events and maintains the current phase
offset between inputs and outputs.
Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) causes a phase
change on the output clocks while the DPLL switches to tracking the selected reference with zero degrees of phase
error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which
includes unfreezing) while locking or locked also causes a PBO event.
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
Phase Monitor
Phase Build-Out in Response to Input Phase Transients
MSR3
register and requests an interrupt if enabled.
OPSTATE
register, which sets the
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