DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 36

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the
internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two
input clocks. When T0CR1:T4MT0 = 1, the T4 DPLL locking capability is disabled, and the T4 phase detector is
configured to compare the T0 DPLL selected reference with the T4 DPLL selected reference. Any input clock can
then be forced to be the T4 DPLL selected reference using the T4FORCE field of MCR4. This feature can be used,
for example, to measure the phase difference between the T0 DPLL’s selected reference and its next highest
priority reference. Software could compute MTIE and TDEV with respect to the T0 DPLL selected reference for any
or all the other input clocks.
When comparing the phase of the T0 and T4 selected references by setting T0CR1:T4MT0 = 1, several details
must be considered. In this mode, the T4 path receives a copy of the T0 selected reference, either directly or
through a divider to 8kHz. If the T4 selected reference is divided down to 8kHz using LOCK8K or DIVN modes (see
Section 7.4.2), the copy of the T0 selected reference is also divided down to 8kHz. If the T4 selected reference is
configured for direct-lock mode, the copy of the T0 selected reference is not divided down and must be the same
frequency as the T4 selected reference. See
Table 7-6
for more details. (While T0CR1:T4MT0 = 1, the T0 path
continues to lock to the T0 selected reference in the manner specified in the corresponding
ICR
register.)
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