DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 118

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Low-Frequency Input Clock Noise Window (NW). For 2kHz, 4kHz, or 8kHz input clocks, this configuration
bit enables a 5% tolerance noise window centered around the expected clock edge location. Noise-induced edges
outside this window are ignored, reducing the possibility of phase hits on the output clocks. This only applies to the
T0 DPLL and should be enabled only when the T0 DPLL is locked to an input and the 180 phase detector is being
used (TEST1.D180=0).
Bit 5: Phase Monitor Enable (PMEN). This configuration bit enables the phase monitor, which measures the
phase error between the input clock reference and the DPLL output. When the DPLL is set for low bandwidth, a
phase transient on the input causes an immediate phase error that is gradually reduced as the DPLL tracks the
input. When the measured phase error exceeds the limit set in the PMLIM field, the phase monitor declares a
phase monitor alarm by setting MSR3:PHMON. See Section 7.7.7.
Bit 4: Phase Monitor to Phase Build-Out Enable (PMPBEN). This bit enables phase build-out in response to
phase hits on the selected reference. See Section 7.7.7.
Bits 3 to 0: Phase Monitor Limit (PMLIM[3:0]). This field is an unsigned integer that specifies the magnitude of
phase error that causes a phase monitor alarm to be declared (PHMON bit in the
monitor limit in nanoseconds is equal to (PMLIM[3:0] + 7) * 156.25, which corresponds to a range of 1094 ns to
3437 ns in 156.25 ns steps. The phase monitor is enabled by setting PMEN=1. See Section 7.7.7.
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
0 = All edges are recognized by the T0 DPLL.
1 = Only edges within the 5% tolerance window are recognized by the T0 DPLL.
0 = Disabled
1 = Enabled
0 = Phase monitor alarm does not trigger a phase build-out event
1 = Phase monitor alarm does trigger a phase build-out event
NW
7
0
—
6
0
PHMON
Phase Monitor Register
76h
PMEN
5
0
PMPBEN
4
0
3
0
MSR3
2
1
PMLIM[3:0]
register). The phase
1
1
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0
0