DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 5

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
List of Tables
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14
Table 6-3. Global Pin Descriptions ............................................................................................................................ 15
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16
Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements..................................................................................... 18
Table 7-2. Input Clock Capabilities ............................................................................................................................ 19
Table 7-3. Locking Frequency Modes ....................................................................................................................... 20
Table 7-4. Default Input Clock Priorities .................................................................................................................... 23
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32
Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 37
Table 7-7. Output Clock Capabilities ......................................................................................................................... 38
Table 7-8. Digital1 Frequencies................................................................................................................................. 40
Table 7-9. Digital2 Frequencies................................................................................................................................. 41
Table 7-10. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) ........................................................ 41
Table 7-11. T0 APLL Frequency Configuration ......................................................................................................... 41
Table 7-12. T0 APLL2 Frequency Configuration ....................................................................................................... 41
Table 7-13. T4 APLL Frequency Configuration ......................................................................................................... 42
Table 7-14. OC1 to OC7 Output Frequency Selection .............................................................................................. 42
Table 7-15. Standard Frequencies for Programmable Outputs ................................................................................ 43
Table 7-16. Equipment Redundancy Methodology ................................................................................................... 46
Table 7-17. External Frame-Sync Mode and Source ................................................................................................ 48
Table 7-18. External Frame-Sync Source ................................................................................................................. 49
Table 8-1. Register Map ............................................................................................................................................ 55
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 127
Table 9-2. JTAG ID Code ........................................................................................................................................ 128
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 129
Table 10-2. DC Characteristics................................................................................................................................ 129
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 130
Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 130
Table 10-5. LVDS Output Pins ................................................................................................................................ 130
Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 131
Table 10-7. Input Clock Timing................................................................................................................................ 133
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 133
Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode............................................................ 133
Table 10-10. SPI Interface Timing ........................................................................................................................... 134
Table 10-11. JTAG Interface Timing........................................................................................................................ 136
Table 10-12. Reset Pin Timing ................................................................................................................................ 137
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 138
Table 12-1. CSBGA Package Thermal Properties, Natural Convection ................................................................. 140
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