DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 47

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
Given this information, if master and slave devices are crosswired with 19.44MHz clocks, for example, the output
clocks at N x 19.44MHz (N = 1, 2, 4, 8, or 16) from the two devices are phase-aligned with one another. Output
clocks at lower frequencies (6.48MHz, 1.544MHz, 2.048MHz, 2kHz, 8kHz, etc.) from the two devices would not
necessarily be phase-aligned. In many systems, lack of phase alignment between the two devices at these clock
rates is not an issue. In some systems, however, the 2kHz and/or 8kHz clocks of the two devices must be aligned
to avoid framing errors during switchover between master and slave.
One way to align the 2kHz and/or 8kHz clocks of the master and slave devices is to configure the slave to lock to a
2kHz or 8kHz output of the master. Another way is to use the external frame-sync signal as described in Section
7.9.2.
7.9.2 Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals
With this method of aligning the 2kHz and 8kHz clocks of the master and slave devices, both a higher speed clock
(such as 6.48MHz or 19.44MHz) and a frame (or multiframe) sync signal from the master are passed to the slave
(and vice versa when their roles are reversed). The higher speed clock from the master is connected to a regular
input clock pin on the slave, such as IC3 or IC4, while the frame-sync signal from the master is connected to a
SYNCn input pin on the slave, such as SYNC1 or SYNC2. The slave locks to the higher speed clock and samples
the frame-sync signal on the associated SYNCn pin. The slave then uses the SYNCn signal to falling-edge align
some or all the output clocks. When the SYNCn signal is a 2kHz clock, output clocks 2kHz and above are falling-
edge aligned. A 4kHz or 8kHz clock can also be used on the SYNCn pins without any changes to the register
configuration, but only output clocks of 8kHz and above are aligned in this case. Phase build-out should be
disabled on the slave (PBOEN = 0 in MCR10) when using SYNCn signals for output clock alignment.
An external frame-sync signal is only allowed to aligh output clocks if the T0 DPLL is locked and the SYNCn signal
is enabled and qualified. Section
7.9.2.1
discusses enable, while Section
7.9.2.4
covers qualification.
7.9.2.1 Enable and SYNCn Pin Selection
Table 7-17
shows how to configure the device for various external frame-sync modes. When MCR3:EFSEN = 0,
external frame sync is disabled. When EFSEN = 1, three different external frame-sync modes are available:
SYNC1 Manual, SYNC1 Auto, and SYNC123.
In SYNC1 Manual mode, external frame sync is enabled on the SYNC1 pin whenever the T0 DPLL is locked,
regardless of which input clock is the selected reference. When the T0 DPLL is not locked, external frame sync is
disabled. In this mode the SYNC2 and SYNC3 pins are ignored.
In SYNC1 Auto mode, external frame sync is automatically enabled on the SYNC1 pin when the T0 DPLL is locked
to the input clock pin specified by FSCR3:SOURCE. If the T0 DPLL is not locked or is locked to a different input
clock than the one specified by the SOURCE field, then external frame sync is disabled. In this mode the SYNC2
and SYNC3 pins are ignored.
In SYNC123 mode, the SYNC1, SYNC2, and SYNC3 pins are each associated with one or more input clock pins
as specified by FSCR1:SYNCSRC. SYNC1 can be associated with IC3 or IC5 or both. SYNC2 can be associated
with IC4 or IC6 or both. SYNC3 is always associated with IC9. When the T0 DPLL is locked to one of the input
clock pins associated with a SYNCn pin, external frame sync is automatically enabled with the corresponding
SYNCn pin as the source. When the T0 DPLL is not locked or is locked to an input clock pin that is not associated
with a SYNCn pin then external frame sync is disabled.
Since SYNC123 mode is always automatic, MCR3:AEFSEN takes on a different meaning in this mode, specifying
whether or not MCR3:EFSEN is automatically cleared when the T0 DPLL’s selected reference changes.
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