DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 61

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 2 to 0: Current DPLL Frequency (FREQ[18:16]). See the
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Frame-Sync Input Monitor Alarm (FSMON). This latched status bit is set to 1 when OPSTATE:FSMON
transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt
request on the INTREQ pin if the FSMON interrupt enable bit is set in the
Bit 6: T4 DPLL Lock Status Change (T4LOCK). This latched status bit is set to 1 when the lock status of the T4
DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when
previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes
again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit
is set in the
Bit 5: Phase Monitor Alarm (PHMON). This latched status bit is set to 1 when the phase monitor alarm limit has
been exceeded (PMLIM field of the
until the threshold is exceeded again. When PHMON is set it can cause an interrupt request on the INTREQ pin if
the PHMON interrupt enable bit is set in the
Bit 4: T4 No Valid Inputs Alarm (T4NOIN). This latched status bit is set to 1 when the T4 DPLL has no valid
inputs available. T4NOIN is cleared when written with a 1 unless the T4 DPLL still has no valid inputs available.
When T4NOIN is set it can cause an interrupt request on the INTREQ pin if the T4NOIN interrupt enable bit is set
in the
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
IER3
register. See Section 7.5.
IER3
FSMON
—
register. See Section 7.7.6.
7
0
7
0
T4LOCK
—
6
0
6
1
FREQ3
Frequency Register 3
07h
MSR3
Master Status Register 3
08h
PHMON
PHMON
—
5
0
5
0
IER3
register). PHMON is cleared when written with a 1 and not set again
register. See Section 7.7.7.
T4NOIN
—
4
0
4
1
FREQ1
—
3
0
—
3
0
register description.
IER3
register. See Section 7.9.2.
—
2
0
2
0
FREQ[18:16]
—
1
0
1
0
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—
0
0
0
0