DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 23

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

7.6
7.6.1 Priority Configuration
During normal operation, the selected reference for the T0 DPLL and the selected reference for the T4 DPLL are
chosen automatically based on the priority rankings assigned to the input clocks in the input priority registers
to IPR5). Each of these registers has priority fields for one or two input clocks. When T4T0 = 0 in the
register, the IPR registers specify the input clock priorities for the T0 DPLL. When T4T0 = 1, the IPR registers
specify the input clock priorities for the T4 DPLL. The default input clock priorities, for both PLLs, are shown in
Table
Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable
for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks.
Table 7-4. Default Input Clock Priorities
7.6.2 Automatic Selection Algorithm
The real-time valid/invalid state of each input clock is maintained in the
selected reference can be marked invalid for phase lock, frequency, or activity. Other input clocks can be
invalidated for frequency or activity.
The reference selection algorithm for each DPLL chooses the highest priority valid input clock to be the selected
reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table
of valid inputs. The top three entries in this table and the selected reference are displayed in the
PTAB2
for the T0 DPLL. When T4T0 = 1, they indicate the highest priority input clocks for the T4 DPLL.
If two or more input clocks are given the same priority number, those inputs are prioritized among themselves using
a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid, the next equal-priority
clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference
becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently
nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equal-
priority inputs have the highest priority.
An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the
mode (REVERT = 1), if an input clock with a higher priority than the selected reference becomes valid, the higher
priority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higher
priority reference does not immediately become the selected reference but does become the highest priority
reference in the priority table (REF1 field in the
highest priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For
many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the
output clocks due to reference switching. The T4 DPLL always operates in revertive mode.
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
INPUT CLOCK
7-4.
IC1
IC2
IC3
IC4
IC5
IC6
IC8
IC9
registers. When T4T0 = 0 in the
Input Clock Priority, Selection, and Switching
DEFAULT
PRIORITY
T0 DPLL
0 (off)
0 (off)
0 (off)
1
2
3
4
5
MCR11
PRIORITY
DEFAULT
T4 DPLL
0 (off)
0 (off)
0 (off)
0 (off)
1
2
3
5
PTAB1
register, these registers indicate the highest priority input clocks
register). (The selection algorithm always switches to the
VALSR1
and
MCR3
VALSR2
register. In revertive
registers. The
PTAB1
23 of 142
MCR11
(IPR1
and