DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 49

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

generator is not synchronized with the FSYNC/MFSYNC 2kHz alignment generator and continues to free-run with
its existing 2kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when SYNCn has a
change of phase position.
7.9.2.6 Frame-Sync Monitor
The frame-sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable
bit (MCR3:EFSEN).
When EFSEN = 1 (external frame sync enabled), the OPSTATE:FSMON bit is set when SYNCn is not qualified
and cleared when SYNCn is qualified. If SYNCn is disqualified, both 2kHz alignment generators are immediately
disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When OPSTATE:FSMON
is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the
If SYNCn immediately stabilizes at a new phase and proper frequency, it is requalified after 64 2kHz cycles
(nominally 32ms). Unless system software intervenes, after SYNCn is requalified the 2kHz alignment generators
will synchronize with SYNCn’s new phase alignment, causing a sudden phase movement on the output clocks.
System software can avoid this sudden phase movement on the output clocks by responding to the FSMON
interrupt within the 32ms window with appropriate action, which might include disabling external frame sync
(MCR3:EFSEN = 0) to prevent the resynchronization of the 2kHz alignment generators with SYNCn, forcing the T0
DPLL into holdover (MCR1:T0STATE = 010) to avoid affecting the output clocks with any other phase hits, and
possibly even disabling the master timing card and promoting the slave timing card to master since the 2kHz signal
from the master should not have such phase movements.
When EFSEN = 0 (external frame sync disabled), OPSTATE:FSMON is set when the negative edge of the
resampled SYNCn signal is outside the window determined by FSCR3:MONLIM relative to the MFSYNC negative
edge (or positive edge if MFSYNC is inverted) and clear when within the window. When OPSTATE:FSMON is set,
the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the
7.9.3 SYNCn Pins
FSYNC and MFSYNC are always produced from the T0 DPLL. The other output clocks can also be configured as
2kHz or 8kHz outputs, derived from the T0 DPLL.
Table 7-18. External Frame-Sync Source
There are three PHASEn[1:0] (n = 1, 2, 3) select fields in the
SYNC1, PHASE2[1:0] is associated with SYNC2, and PHASE3[1:0] is associated with SYNC3. All three SYNCn
inputs can have their timing adjusted to account for frame-sync signal vs. clock signal delay differences in each
path.
When this function is enabled with FSCR3.SOURCE = 11XX, MCR3.AEFSEN, and MCR3.EFSEN, the monitoring
and qualification function described in Section
19-4617; Rev 5; 8/10
____________________________________________________________________________________________ DS3102
SYNCSRC[2:0]
0XX
1X0
10X
1X1
11X
REFERENCE
SELECTED
IC3 or IC5
IC4 or IC6
IC9 or IC2
IC3
IC4
IC9
IC5
IC6
IC2
EXTERNAL FRAME-
7.9.2
SYNC SOURCE
SYNC1
SYNC2
SYNC3
SYNC1
SYNC2
SYNC3
SYNC1
SYNC2
SYNC3
is only performed on the selected SYNCn input pin.
FSCR2
register. PHASE1[1:0] is associated with
IER3
register.
IER3
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register.