DS3102GN Maxim Integrated Products, DS3102GN Datasheet - Page 25

• Manufacturer Part Number: DS3102GN
• Description: Timers & Support Products Stratum 3 Timing Car d IC SEC-EEC Timing
• Manufacturer: Maxim Integrated Products

____________________________________________________________________________________________ DS3102
In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the
selected reference whether it is valid. Unlike forced reference selection (Section 7.6.3) this mode controls the
PTAB1:SELREF field directly and is, therefore, not affected by the state of the MCR3:REVERT bit. During external
reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2, and REF3 fields in the
PTAB
registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the
automatic selection logic. External reference switching mode only affects the T0 DPLL.
7.6.6 Output Clock Phase Continuity During Reference Switching
If phase build-out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than
30ppm, the device always complies with the GR-1244-CORE requirement that the rate of phase change must be
less than 81ns per 1.326ms during reference switching.
7.6.7 Frequency Monitoring Hysteresis Required by Telcordia GR-1244-CORE
For stratum 3 and stratum 3E applications, taking all Telcordia GR-1244-CORE requirements together, the DS3102
must accept input clocks with frequency offsets of less than ±9.2ppm and must reject input clocks with frequency
offsets of more than ±12.0ppm. In between 9.2ppm and 12.0ppm the actual accept and reject thresholds must be
separated by at least 0.46ppm.
To realize GR-1244-CORE compliant thresholds for stratum 3 and stratum 3E, the appropriate settings are
ILIMIT.HARD=2, DLIMIT1,2.HARDLIM=0x99, SRLIMIT.HARD=3.
An accept threshold greater than 9.2ppm is provided by the ILIMIT.HARD value. Setting ILIMIT.HARD=2 gives a
value of 11.43ppm according to the register description, but the actual threshold is halfway between the values
given in the register description. Therefore ILIMIT.HARD=2 is halfway between 7.62ppm and 11.43ppm. This gives
an accept threshold of 9.53ppm.
A reject threshold less than 12.0ppm is provided by the DLIMIT1,2.HARDLIM value. If the frequency of the selected
reference exceeds this limit the DPLL does not track it and goes out of lock. After a loss-of-lock timeout (specified
by PHLKTO) the DPLL rejects the input.
Finally, the SRLIMIT.HARD=3 value provides a backup reject threshold in case the selected reference frequency
goes off frequency too rapidly. As with ILIMIT.HARD, the actual threshold is halfway between the values given in
the register description. Therefore SRLIMIT.HARD=3 is halfway between 11.43ppm and 15.24ppm. This gives a
backup reject threshold of 13.34ppm.
19-4617; Rev 5; 8/10
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