ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 8

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority
interrupts (IVG15–14) are recommended to be reserved for
Table 3. Core Event Controller (CEC)
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processors provide a default mapping, the user
Table 4. Peripheral Interrupt Assignment
Priority (0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Peripheral Interrupt Event
PLL Wakeup Interrupt
DMA Error 0 (generic)
DMAR0 Block Interrupt
DMAR1 Block Interrupt
DMAR0 Overflow Error
DMAR1 Overflow Error
PPI Error
MAC Status
SPORT0 Status
SPORT1 Status
PTP Error Interrupt
Reserved
UART0 Status
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General-Purpose Interrupt 7
General-Purpose Interrupt 8
General-Purpose Interrupt 9
General-Purpose Interrupt 10
General-Purpose Interrupt 11
General-Purpose Interrupt 12
General-Purpose Interrupt 13
General-Purpose Interrupt 14
General-Purpose Interrupt 15
General Purpose
Interrupt (at Reset)
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
Rev. A | Page 8 of 72 | August 2010
Peripheral
Interrupt ID
0
1
2
3
4
5
6
7
8
9
10
11
12
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processors.
describes the inputs to the CEC, identifies their names in the
event vector table (EVT), and lists their priorities.
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (SIC_IARx).
and the default mappings into the CEC.
Default Core
Interrupt ID
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4
describes the inputs into the SIC
SIC Registers
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR0
IAR1
IAR1
IAR1
IAR1
IAR1
NMI
EVT Entry
EMU
RST
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
IMASK0 and ISR0
Table 3