ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 18

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The CLKBUF signal is an output signal, which is a buffered ver-
sion of the input clock. This signal is particularly useful in
Ethernet applications to limit the number of required clock
sources in the system. In this type of application, a single
25 MHz or 50 MHz crystal may be applied directly to the pro-
cessor. The 25 MHz or 50 MHz output of CLKBUF can then be
connected to an external Ethernet MII or RMII PHY device.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in
system peripheral clock (SCLK) are derived from the input
clock (CLKIN) signal. An on-chip PLL is capable of multiplying
the CLKIN signal by a programmable 5× to 64× multiplication
factor (bounded by specified minimum and maximum VCO
frequencies). The default multiplier is 6×, but it can be modified
by a software instruction sequence.
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register. The maximum allowed CCLK and
SCLK rates depend on the applied voltages V
V
specified by the part’s speed grade. The CLKOUT signal reflects
the SCLK frequency to the off-chip world. It belongs to the
SDRAM interface, but it functions as reference signal in other
timing specifications as well. While active by default, it can be
disabled using the EBIU_SDGCTL and EBIU_AMGCTL
registers.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
CLKIN
DDMEM
Table 7
REQUIRES PLL SEQUENCING
, the VCO is always permitted to run up to the frequency
“FINE” ADJUSTMENT
illustrates typical system clock ratios.
5u to 64u
Figure 6. Frequency Modification Methods
PLL
Figure
VCO
6, the core clock (CCLK) and
SCLK
“COARSE” ADJUSTMENT
÷ 1 to 15
÷ 1, 2, 4, 8
. The SSEL value can be
ON-THE-FLY
DDINT
, V
Rev. A | Page 18 of 72 | August 2010
CCLK
SCLK
DDEXT
, and
Table 7. Example System Clock Ratios
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
fast core frequency modifications.
Table 8. Core Clock Ratios
The maximum CCLK frequency not only depends on the part's
speed grade (see
voltage. See
(SCLK) depends on the chip package and the applied V
V
BOOTING MODES
The processor has several mechanisms (listed in
automatically loading internal and external memory after a
reset. The boot mode is defined by three BMODE input bits
dedicated to this purpose. There are two categories of boot
modes. In master boot modes the processor actively loads data
from parallel or serial memories. In slave boot modes the pro-
cessor receives data from external host devices.
The boot modes listed in
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time. The BMODE
bits of the reset configuration register, sampled during power-
on resets and software-initiated resets, implement the modes
shown in
Table 9. Booting Modes
Signal Name
SSEL3–0
0010
0110
1010
Signal Name
CSEL1–0
00
01
10
11
BMODE2–0 Description
000
001
010
DDEXT
8. This programmable core clock capability is useful for
, and V
Table
Table 12
DDMEM
Idle - No boot
Boot from 8- or 16-bit external flash memory
Boot from internal SPI memory
9.
Divider Ratio
VCO/SCLK
2:1
6:1
10:1
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
Page
voltages (see
for details. The maximal system clock rate
70), it also depends on the applied V
Table 9
VCO
100
300
400
VCO
300
300
400
200
provide a number of mecha-
Table 14 on Page
Example Frequency Ratios
Example Frequency Ratios
(MHz)
(MHz)
SCLK
50
50
40
CCLK
300
150
100
25
Table
26).
9) for
DDINT
DDINT
,