ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 47
![no-image](/images/manufacturer_photos/0/0/57/analog_devices_inc_sml.jpg)
ADSP-BF514KSWZ-4F4
Manufacturer Part Number
ADSP-BF514KSWZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514KSWZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514KSWZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514KSWZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 41
Table 41. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
DSOE
DSDHI
DDSPID
HDSPID
HSPID
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
CPHA = 1
CPHA = 0
Figure 26
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
SPIxMISO
(OUTPUT)
SPIxMOSI
SPIxMISO
(OUTPUT)
SPIxMOSI
SPIxSCK
(INPUT)
(INPUT)
(INPUT)
(INPUT)
t
DSOE
describe SPI port slave operations.
t
DSOE
t
SDSCI
t
SSPID
t
DDSPID
t
SPICLS
Figure 26. Serial Peripheral Interface (SPI) Port—Slave Timing
t
HDSPID
Rev. A | Page 47 of 72 | August 2010
t
SPICHS
t
HDSPID
t
HSPID
t
DDSPID
Min
2 × t
2 × t
4 × t
2 × t
2 × t
2 × t
1.6
2
0
0
0
t
SSPID
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
1.8V Nominal
t
–1.5
–1.5
–1.5
–1.5
DDSPID
–1.5
–1.5
V
t
SPICLK
DDEXT
Max
12
11
10
t
HSPID
Min
2 × t
2 × t
4 × t
2 × t
2 × t
2 × t
1.6
1.6
0
0
0
t
HDS
t
t
DSDHI
DSDHI
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
2.5/3.3V Nominal
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
V
t
SPITDS
DDEXT
10.3
9
10
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns