ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 12

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
The timers can generate interrupts to the processor core provid-
ing periodic events for synchronization, either to the system
clock or to a count of external signals.
In addition to the eight general-purpose programmable timers,
a ninth timer is also provided. This extra timer is clocked by the
internal processor clock and is typically used as a system tick
clock for generation of operating system periodic interrupts.
3-PHASE PWM
Features of the 3-phase PWM generation unit are:
The processors integrate a flexible and programmable 3-phase
PWM waveform generator that can be programmed to generate
the required switching patterns to drive a 3-phase voltage
source inverter for ac induction (ACIM) or permanent magnet
synchronous (PMSM) motor control. In addition, the PWM
block contains special functions that considerably simplify the
generation of the required PWM switching patterns for control
of the electronically commutated motor (ECM) or brushless dc
motor (BDCM). Software can enable a special mode for
switched reluctance motors (SRM).
The six PWM output signals consist of three high-side drive sig-
nals (PWM_AH, PWM_BH, and PWM_CH) and three
low-side drive signals (PWM_AL, PWM_BL, and PWM_CL).
The polarity of the generated PWM signal be set with software,
so that either active HI or active LO PWM patterns can be
produced.
The switching frequency of the generated PWM pattern is pro-
grammable using the 16-bit PWMTM register. The PWM
generator can operate in single update mode or double update
mode. In single update mode the duty cycle values are program-
mable only once per PWM period, so that the resultant PWM
patterns are symmetrical about the midpoint of the PWM
period. In the double update mode, a second updating of the
PWM registers is implemented at the midpoint of the PWM
period. In this mode, it is possible to produce asymmetrical
PWM patterns that produce lower harmonic distortion in
3-phase PWM inverters.
• 16-bit center-based PWM generation unit
• Programmable PWM pulse width
• Single/double update modes
• Programmable dead time and switching frequency
• Twos-complement implementation which permits smooth
• Possibility to synchronize the PWM generation to an exter-
• Special provisions for BDCM operation (crossover and
• Wide variety of special switched reluctance (SR) operating
• Output polarity and clock gating control
• Dedicated asynchronous PWM shutdown signal
transition to full ON and full OFF states
nal synchronization
output enable functions)
modes
Rev. A | Page 12 of 72 | August 2010
GENERAL-PURPOSE (GP) COUNTER
A 32-bit GP counter is provided that can sense 2-bit quadrature
or binary codes as typically emitted by industrial drives or man-
ual thumb wheels. The counter can also operate in general-
purpose up/down count modes. Then, count direction is either
controlled by a level-sensitive input signal or by two edge
detectors.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three signals have a programmable debouncing
circuit.
An internal signal forwarded to the GP timer unit enables one
timer to measure the intervals between count events. Boundary
registers enable auto-zero operation or simple system warning
by interrupts when programmable count values are exceeded.
SERIAL PORTS
The ADSP-BF51x processors incorporate two dual-channel syn-
chronous serial ports (SPORT0 and SPORT1) for serial and
multiprocessor communications. The SPORTs support the fol-
lowing features:
• I
• Bidirectional operation—Each SPORT has two sets of inde-
• Buffered (8-deep) transmit and receive ports—Each port
• Clocking—Each transmit and receive port can either use an
• Word length—Each SPORT supports serial data words
• Framing—Each transmit and receive port can run with or
• Companding in hardware—Each SPORT can perform
• DMA operations with single-cycle overhead—Each SPORT
pendent transmit and receive signals, enabling eight
channels of I
has a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
external serial clock or generate its own, in frequencies
ranging from (f
from 3 to 32 bits in length, transferred most-significant-bit
first or least-significant-bit first.
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulse widths and early or late
frame sync.
A-law or μ-law companding according to ITU recommen-
dation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without
additional latencies.
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
2
S capable operation.
2
S stereo audio.
SCLK
/131,070) Hz to (f
SCLK
/2) Hz.