ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 13

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL PERIPHERAL INTERFACE (SPI) PORTS
The processors have two SPI-compatible ports (SPI0 and SPI1)
that enable the processor to communicate with multiple SPI-
compatible devices.
The SPI interface uses three signals for transferring data: two
data signals (master output-slave input–MOSI, and master
input-slave output–MISO) and a clock signal (serial
clock–SCK). An SPI chip select input signal (SPIxSS) lets other
SPI devices select the processor, and multiple SPI chip select
output signals let the processor select other SPI devices. The SPI
select signals are reconfigured general-purpose I/O signals.
Using these signals, the SPI port provides a full-duplex, syn-
chronous serial interface, which supports both master/slave
modes and multimaster environments.
The SPI port baud rate and clock phase/polarities are program-
mable, and it has an integrated DMA channel, configurable to
support transmit or receive data streams. The SPI’s DMA chan-
nel can only service unidirectional accesses at any given time.
The SPI port clock rate is calculated as:
Where the 16-bit SPI_BAUD register contains a value of 2
to 65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sam-
pling of data on the two serial data lines.
UART PORTS
The ADSP-BF51x processors provide two full-duplex universal
asynchronous receiver/transmitter (UART) ports, which are
fully compatible with PC-standard UARTs. Each UART port
provides a simplified UART interface to other peripherals or
hosts, supporting full-duplex, DMA-supported, asynchronous
transfers of serial data. A UART port includes support for five to
eight data bits, one or two stop bits, and none, even, or odd par-
ity. Each UART port supports two modes of operation:
• Interrupts—Each transmit and receive port generates an
• Multichannel capability—Each SPORT supports 128 chan-
• PIO (programmed I/O)—The processor sends or receives
• DMA (direct memory access)—The DMA controller trans-
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer, or buffers,
through DMA.
nels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
data by writing or reading I/O mapped UART registers.
The data is double-buffered on both transmit and receive.
fers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. The UART has two dedicated
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
SPI Clock Rate
=
----------------------------------- -
2
×
SPI_BAUD
f
SCLK
Rev. A | Page 13 of 72 | August 2010
Each UART port's baud rate, serial data format, error code gen-
eration and status, and interrupts are programmable:
The UART port’s clock rate is calculated as:
Where the 16-bit UART_Divisor comes from the UART_DLH
(most significant 8 bits) and UART_DLL (least significant
8 bits) registers.
In conjunction with the general-purpose timer functions, auto-
baud detection is supported.
The capabilities of the UARTs are further extended with sup-
port for the infrared data association (IrDA®) serial infrared
physical layer link specification (SIR) protocol.
2-WIRE INTERFACE (TWI)
The processors include a TWI module for providing a simple
exchange method of control data between multiple devices. The
TWI is compatible with the widely used I
TWI module offers the capabilities of simultaneous master and
slave operation, support for both 7-bit addressing and multime-
dia data arbitration. The TWI interface utilizes two signals for
transferring clock (SCL) and data (SDA) and supports the pro-
tocol at speeds up to 400k bits/sec. The TWI interface signals
are compatible with 5 V logic levels.
Additionally, the processor’s TWI module is fully compatible
with serial camera control bus (SCCB) functionality for easier
control of various CMOS camera sensor devices.
REMOVABLE STORAGE INTERFACE (RSI)
The RSI controller, available on the ADSP-BF514, ADSP-BF516,
ADSP-BF518, and ADSP-BF518F acts as the host interface for
multi-media cards (MMC), secure digital memory cards (SD Card),
secure digital input/output cards (SDIO), and CE-ATA hard disk
drives. The following list describes the main features of the RSI
controller.
• Supporting bit rates ranging from (f
• Supporting data formats from seven to 12 bits per frame.
• Both transmit and receive operations can be configured to
• Support for a single MMC, SD memory, SDIO card or CE-
• Support for 1-bit and 4-bit SD modes
• Support for 1-bit, 4-bit and 8-bit MMC modes
• Support for 4-bit and 8-bit CE-ATA hard disk drives
• A ten-signal external interface with clock, command, and
• Card detection using one of the data signals
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates.
(f
generate maskable interrupts to the processor.
ATA hard disk drive
up to eight data lines
SCLK
/16) bits per second.
UART Clock Rate
=
---------------------------------------------- -
16 UART_Divisor
×
f
SCLK
SCLK
2
C
®
/1,048,576) to
bus standard. The