ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 16

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
of clocking to each of the processor peripherals also reduces
power consumption. See
settings for each mode.
Table 5. Power Settings
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Power Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the full-on mode is
entered. DMA access is available to appropriately configured
L1 memories.
In the active mode, it is possible to disable the PLL through the
PLL control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting wakeup causes the processor
to sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor transitions to
the full on mode. If BYPASS is enabled, the processor transi-
tions to the active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Deep Sleep Operating Mode—Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but cannot access internal
resources or external memory. This powered-down mode can
only be exited by assertion of the reset interrupt (RESET) or by
Mode/State PLL
Full On
Active
Sleep
Deep Sleep
Hibernate
Enabled No
Enabled/
Disabled
Enabled —
Disabled —
Disabled —
PLL
Bypassed
Yes
Table 5
for a summary of the power
Disabled Enabled On
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
Disabled Disabled On
Disabled Disabled Off
System
Clock
(SCLK)
Rev. A | Page 16 of 72 | August 2010
Core
Power
an asynchronous interrupt generated by the RTC. When in deep
sleep mode, an RTC asynchronous interrupt causes the proces-
sor to transition to the Active mode. Assertion of RESET while
in deep sleep mode causes the processor to transition to the full
on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and system
blocks (SCLK). Any critical information stored internally
(memory contents, register contents, etc.) must be written to a
non-volatile storage device prior to removing power if the pro-
cessor state is to be preserved. Writing b#00 to the FREQ bits in
the VR_CTL register also causes EXT_WAKE to transition low,
which can be used to signal an external voltage regulator to shut
down.
Since V
nals three-state, unless otherwise specified. This allows other
devices that may be connected to the processor to still have
power applied without drawing unwanted current.
The Ethernet module can signal an external regulator to wake
up using EXT_WAKE. If PF15 does not connect as a PHYINT
signal to an external PHY device, it can be pulled low by any
other device to wake the processor up. The processor can also be
woken up by a real-time clock wakeup event or by asserting the
RESET pin. All hibernate wakeup events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register. The EXT_WAKE signal is provided to indicate the
occurrence of wakeup events.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables may be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register controls
whether or not SDRAM operates in self-refresh mode, which
allows it to retain its content while the processor is in hiberna-
tion and through the subsequent reset sequence.
Power Savings
As shown in
power domains, which maximizes flexibility while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains, but all domains
must be powered according to the appropriate
table for processor Operating Conditions; even if the fea-
ture/peripheral is not used.
DDEXT
Table
is still supplied in this mode, all of the external sig-
6, the processors support up to six different
Specifications