ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
10/100 ETHERNET MAC
The ADSP-BF516/ADSP-BF516F and ADSP-BF518/ADSPBF518F
processors offer the capability to directly connect to a network by
way of an embedded fast Ethernet media access controller (MAC)
that supports both 10-BaseT (10M bits/sec) and 100-BaseT (100M
bits/sec) operation. The 10/100 Ethernet MAC peripheral on the
processor is fully compliant to the IEEE 802.3-2002 standard and it
provides programmable features designed to minimize supervision,
bus use, or message processing by the rest of the processor system.
Some standard features are:
Some advanced features are:
• Card interface clock generation from SCLK
• SDIO interrupt and read wait features
• CE-ATA command completion signal recognition and
• Support of MII and RMII protocols for external PHYs
• Full duplex and half duplex modes
• Data framing and encapsulation: generation and detection
• Media access management (in half-duplex operation): col-
• Flow control (in full-duplex operation): generation and
• Station management: generation of MDC/MDIO frames
• Operating range for active and sleep operating modes, see
• Internal loopback from transmit to receive
• Buffered crystal output to external PHY for support of a
• Automatic checksum computation of IP header and IP
• Independent 32-bit descriptor-driven receive and transmit
• Frame status delivery to memory through DMA, including
• Tx DMA support for separate descriptors for MAC header
• Convenient frame alignment modes support even 32-bit
• Programmable Ethernet event interrupt supports any com-
disable
of preamble, length padding, and FCS
lision and contention handling, including control of
retransmission of collision frames and of back-off timing
detection of pause frames
for read-write access to PHY registers
Table 46 on Page 51
single crystal system
payload fields of Rx frames
DMA channels
frame completion semaphores for efficient buffer queue
management in software
and payload to eliminate buffer copy operations
alignment of encapsulated receive or transmit IP packet
data in memory after the 14-byte MAC header
bination of:
• Selected receive or transmit frame status conditions
• PHY interrupt condition
• Wakeup frame detected
and
Table 47 on Page 51
Rev. A | Page 14 of 72 | August 2010
IEEE 1588 SUPPORT
The IEEE 1588 standard is a precision clock synchronization
protocol for networked measurement and control systems. The
ADSP-BF518/ADSP-BF518F processors include hardware sup-
port for IEEE 1588 with an integrated precision time protocol
synchronization engine (PTP_TSYNC). This engine provides
hardware assisted time stamping to improve the accuracy of
clock synchronization between PTP nodes. The main features of
the PTP_SYNC engine are:
PORTS
Because of the rich set of peripherals, the processors group the
many peripheral signals to four ports—port F, port G, port H,
and port J. Most of the associated pins/balls are shared by multi-
ple signals. The ports function as multiplexer controls.
General-Purpose I/O (GPIO)
The ADSP-BF51x processors have 40 bidirectional, general-
purpose I/O (GPIO) signals allocated across three separate
GPIO modules—PORTFIO, PORTGIO, and PORTHIO, associ-
ated with Port F, Port G, and Port H, respectively. Each
• 47 MAC management statistics counters with selectable
• Programmable receive address filters, including a 64-bin
• Advanced power management supporting unattended
• System wakeup from sleep operating mode upon magic
• Support for 802.3Q tagged VLAN frames
• Programmable MDC clock rate and preamble suppression
• In RMII operation, seven unused signals may be config-
• Support for both IEEE 1588-2002 and IEEE 1588-2008 pro-
• Hardware assisted time stamping capable of up to 12.5 ns
• Lock adjustment
• Programmable PTM message support
• Dedicated interrupts
• Programmable alarm
• Multiple input clock sources (SCLK, MII clock, external
• Programmable pulse per second (PPS) output
• Auxiliary snapshot to time stamp external events
clear-on-read behavior and programmable interrupts on
half maximum value
address hash table for multicast and/or unicast frames, and
programmable filter modes for broadcast, multicast, uni-
cast, control, and damaged frames
transfer of receive and transmit frames and status to/from
external memory via DMA during low power sleep mode
packet or any of four user-definable wakeup frame filters
ured as GPIO signals for other purposes
tocol standards
resolution
clock)
• Selected MAC management counter(s) at half-full
• DMA descriptor error