ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 15

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

GPIO-capable signal shares functionality with other peripherals
via a multiplexing scheme; however, the GPIO functionality is
the default state of the device upon power-up. Neither GPIO
output nor input drivers are active by default. Each general-pur-
pose port signal can be individually controlled by manipulation
of the port control, status, and interrupt registers:
PARALLEL PERIPHERAL INTERFACE (PPI)
The ADSP-BF51x processors provide a parallel peripheral inter-
face (PPI) that can connect directly to parallel analog-to-digital
and digital-to-analog converters, ITU-R-601/656 video encod-
ers and decoders, and other general-purpose peripherals. The
PPI consists of a dedicated input clock signal, up to three frame
synchronization signals, and up to 16 data signals.
In ITU-R-656 modes, the PPI receives and parses a data stream
of 8-bit or 10-bit data elements. On-chip decode of embedded
preamble control and synchronization information
is supported.
Three distinct ITU-R-656 modes are supported:
• GPIO direction control register—Specifies the direction of
• GPIO control and status registers—The processor employs
• GPIO interrupt mask registers—The two GPIO interrupt
• GPIO interrupt sensitivity registers—The two GPIO inter-
• Active video only mode—The PPI does not read in any
each individual GPIO signal as input or output.
a “write one to modify” mechanism that allows any combi-
nation of individual GPIO signals to be modified in a single
instruction, without affecting the level of any other GPIO
signals. Four control registers are provided. One register is
written in order to set signal values, one register is written
in order to clear signal values, one register is written in
order to toggle signal values, and one register is written in
order to specify a signal value. Reading the GPIO status
register allows software to interrogate the sense of the
signals.
mask registers allow each individual GPIO signal to func-
tion as an interrupt to the processor. Similar to the two
GPIO control registers that are used to set and clear indi-
vidual signal values, one GPIO interrupt mask register sets
bits to enable interrupt function, and the other GPIO inter-
rupt mask register clears bits to disable interrupt function.
GPIO signals defined as inputs can be configured to gener-
ate hardware interrupts, while output signals can be
triggered by software interrupts.
rupt sensitivity registers specify whether individual signals
are level- or edge-sensitive and specify—if edge-sensitive—
whether just the rising edge or both the rising and falling
edges of the signal are significant. One register selects the
type of sensitivity, and one register selects which edges are
significant for edge-sensitivity.
data between the End of Active Video (EAV) and Start of
Active Video (SAV) preamble symbols, or any data present
during the vertical blanking intervals. In this mode, the
control byte sequences are not stored to memory; they are
filtered by the PPI.
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Rev. A | Page 15 of 72 | August 2010
Though not explicitly supported, ITU-R-656 output functional-
ity can be achieved by setting up the entire frame structure
(including active video, blanking, and control information) in
memory and streaming the data out the PPI in a frame sync-less
mode. The processor’s 2-D DMA features facilitate this transfer
by allowing the static frame buffer (blanking and control codes)
to be placed in memory once, and simply updating the active
video information on a per-frame basis.
The general-purpose modes of the PPI are intended to suit a
wide variety of data capture and transmission applications. The
modes are divided into four main categories, each allowing up
to 16 bits of data transfer per PPI_CLK cycle:
These modes support ADC/DAC connections, as well as video
communication with hardware signalling. Many of the modes
support more than one level of frame synchronization. If
desired, a programmable delay can be inserted between asser-
tion of a frame sync and reception/transmission of data.
CODE SECURITY WITH LOCKBOX SECURE
TECHNOLOGY
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox
include:
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets.
DYNAMIC POWER MANAGEMENT
The ADSP-BF51x processors provide four operating modes,
each with a different performance/power profile. In addition,
dynamic power management provides the control functions to
dynamically alter the processor core supply voltage, further
reducing power dissipation. When configured for a 0 V core
supply voltage, the processor enters the hibernate state. Control
• Data receive with internally generated frame syncs
• Data receive with externally generated frame syncs
• Data transmit with internally generated frame syncs
• Data transmit with externally generated frame syncs
• Vertical blanking only mode—The PPI only transfers verti-
• Entire field mode—The entire incoming bitstream is read
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
cal blanking interval (VBI) data, as well as horizontal
blanking information and control byte sequences on
VBI lines.
in through the PPI. This includes active video, control pre-
amble sequences, and ancillary data that may be embedded
in horizontal and vertical blanking intervals.
®
secure technology. Key features