ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 26

• Manufacturer Part Number: ADSP-BF514KSWZ-4F4
• Description: Low-Pwr BF Proc W/flash & Cnsmr Conctvty
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF514KSWZ-4F4

• Interface: I²C, PPI, RSI, SPI, SPORT, UART/USART
• Clock Rate: 400MHz
• Non-volatile Memory: FLASH (4Mbit)
• On-chip Ram: 116kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.30V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
• Architecture: Modified Harvard
• Format: Fixed Point
• Clock Freq (max): 400MHz
• Device Input Clock Speed: 400MHz
• Ram Size: 48KB
• Program Memory Size: 1024KB
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 176
• Package Type: LQFP EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
Table 11
register. Set this register prior to using the TWI port.
Table 11. TWI_DT Field Selections and V
Table 12
clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as
not to exceed the maximum core clock and system clock.
Table 13
Table 12. Core Clock (CCLK) Requirements
1
2
Table 13. Phase-Locked Loop Operating Conditions
1
Table 14. SCLK Conditions
1
Parameter
f
Parameter
f
f
TWI_DT
000 (default)
001
010
011
100
101
110
111 (reserved)
Parameter
f
f
See the
Applies only to 400 MHz instruction rates. See the
VCO
The speed grade of a given part is printed on the chip’s package as shown in
SCLK
SCLK
f
CCLK
CCLK
SCLK
must be less than or equal to f
Ordering Guide on Page
shows settings for TWI_DT in the NONGPIO_DRIVE
describes the timing requirements for the processor
describes phase-locked loop operating conditions.
1
Voltage Controlled Oscillator (VCO) Frequency
CLKOUT/SCLK Frequency (V
Minimum)
CLKOUT/SCLK Frequency (V
Core Clock Frequency (V
Core Clock Frequency (V
V
3.3
1.8
2.5
1.8
3.3
1.8
2.5
—
70.
DDEXT
CCLK
and is subject to additional restrictions for SDRAM interface operation. See
Nominal
Ordering Guide on Page
DDINT
DDINT
DDINT
DDINT
DDEXT
1
≥ 1.330 V
< 1.330 V)
=1.330 V Minimum)
=1.164 V Minimum)
/V
Rev. A | Page 26 of 72 | August 2010
BUSTWI
—
V
2.97
1.7
2.97
2.97
4.5
2.25
2.25
BUSTWI
Minimum
70.
Figure 7 on Page 31
80
80
Max
2
1.8 V Nominal
Min
70
Nominal Voltage Setting Max
1.400 V
1.225 V
V
DDEXT
and can also be seen on the
/V
V
3.3
1.8
3.3
3.3
5
2.5
2.5
—
BUSTWI
DDMEM
Nominal
Table 31 on Page
Max
100
80
Ordering Guide on Page
2.5 or 3.3 V Nominal
Max
Speed Grade
400
300
V
3.63
1.98
3.63
3.63
5.5
2.75
2.75
—
V
36.
BUSTWI
DDEXT
/V
Maximum
DDMEM
1
70.
Unit
MHz
MHz
Unit
MHz
MHz
MHz
Unit
Unit
V
V
V
V
V
V
V
—