ADSP-BF514KSWZ-4F4 Analog Devices Inc, ADSP-BF514KSWZ-4F4 Datasheet - Page 49
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ADSP-BF514KSWZ-4F4
Manufacturer Part Number
ADSP-BF514KSWZ-4F4
Description
Low-Pwr BF Proc W/flash & Cnsmr Conctvty
Manufacturer
Analog Devices Inc
Series
Blackfin®r
Type
Fixed Pointr
Datasheets
1.ADSP-BF531SBSTZ400.pdf
(12 pages)
2.ADSP-BF512KSWZ-3.pdf
(68 pages)
3.ADSP-BF514KSWZ-4F4.pdf
(72 pages)
Specifications of ADSP-BF514KSWZ-4F4
Interface
I²C, PPI, RSI, SPI, SPORT, UART/USART
Clock Rate
400MHz
Non-volatile Memory
FLASH (4Mbit)
On-chip Ram
116kB
Voltage - I/o
1.8V, 2.5V, 3.3V
Voltage - Core
1.30V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
176-LQFP Exposed Pad, 176-eLQFP, 176-HLQFP
Architecture
Modified Harvard
Format
Fixed Point
Clock Freq (max)
400MHz
Device Input Clock Speed
400MHz
Ram Size
48KB
Program Memory Size
1024KB
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
176
Package Type
LQFP EP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADSP-BF514KSWZ-4F4
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Timer Cycle Timing
Table 44
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 44. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
WL
WH
TIS
TIH
HTO
TOD
ADSP-BF512/BF512F, BF514/BF514F, BF516/BF516F, BF518/BF518F
and
SCLK
Figure 29
Timer Pulse Width Input Low (Measured In SCLK Cycles)
Timer Pulse Width Input High (Measured In SCLK Cycles)
Timer Input Setup Time Before CLKOUT Low
Timer Input Hold Time After CLKOUT Low
Timer Pulse Width Output (Measured In SCLK Cycles)
Timer Output Update Delay After CLKOUT High
/2) MHz.
TMRx OUTPUT
TMRx INPUT
CLKOUT
describe timer expired operations. The
Rev. A | Page 49 of 72 | August 2010
t
2
TIS
Figure 29. Timer Cycle Timing
2
t
WH
,t
WL
t
TIH
1
1
Min
t
t
10
–2
t
SCLK
SCLK
SCLK
t
TOD
– 1.5
1.8V Nominal
V
DDEXT
Max
(2
6
32
t
HTO
–1)t
SCLK
Min
t
t
7
–2
t
SCLK
SCLK
SCLK
– 1
2.5/3.3V Nominal
V
DDEXT
Max
(2
6
32
–1)t
SCLK
Unit
ns
ns
ns
ns
ns
ns