IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 75

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Example Design Walkthrough
Understanding the Example Design and Testbench
Figure 5–1. Example Testbench Block Diagram for non-AFI mode.
Running the Example Testbench from Your Simulator
© March 2009 Altera Corporation
f
1
test_complete
pnf_per_byte
pnf
For further information refer to
Hardware Using the Example
The auto-generated generic SDRAM model may be used as a placeholder for a
specific memory vendor supplied model. For information on how to replace the
generic model with a vendor specific model, refer to “Perform RTL/Functional
Simulation (Optional)” in
GX, and Arria GX
Figure 5–1 on page 5–3
mode.
After you generate the testbench, you can run it directly from your simulation tool.
Before running a simulation directly from your simulation tool, you must run the
simulation once from the Quartus II software to generate the *.do ModelSim file. To
do this, click Run EDA Simulation Tool on the Tools menu and select EDA RTL
Simulation.
You can follow these steps to run the simulation from your simulation tool:
1. Launch ModelSim-Altera.
2. On the File menu, click Change Directory.
3. Select <your project name>/simulation/modelsim and click OK.
4. On the Tools menu, click Execute Macro.
5. Select <your project name>_run_msim_rtl_verilog.do and click OK.
Example Testbench
global_reset_n
clock_source
Example Design / dut
Devices.
High-Performance Controller
shows the testbench and the example design for non-AFI
Encrypted
Calibration Logic
Clock
Reset
and
PLL
DLL
AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II
Driver.
AN 380: Test DDR or DDR2 SDRAM Interfaces on
Encrypted
Controller
Memory
DDR and DDR2 SDRAM High-Performance Controller User Guide
ALTMEMPHY
Write
Read
Addr
Cmd
Path
Path
Path
and
5–3