IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 56
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
IPR-SDRAM/HPDDR
Manufacturer Part Number
IPR-SDRAM/HPDDR
Description
IP CORE Renewal Of IP-SDRAM/HPDDR
Manufacturer
Altera
Datasheet
1.IP-SDRAMHPDDR.pdf
(88 pages)
Specifications of IPR-SDRAM/HPDDR
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
Stratix FPGAs, Quartus II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
- Current page: 56 of 88
- Download datasheet (4Mb)
4–28
DDR and DDR2 SDRAM High-Performance Controller User Guide
3. The user logic requests a third read to a different address, of size 1 (4 on the
4. The controller issues the necessary memory command and address signals to the
5. The controller asserts the control_doing_rd signal to indicate to the
6. The ALTMEMPHY megafunction issues the read commands to the memory and
7. The ALTMEMPHY megafunction returns data to the controller after
8. The controller returns the read data to the user by asserting the
Half Rate Read, Avalon-MM Interface Mode—Non-Consecutive Read
Figure 4–11 on page 4–29
size. In half-rate mode, the controller allows you to use burst size 1, which
corresponds to a complete memory burst of 4.
memory side). The local_ready signal remains asserted, which indicates that
the controller has accepted the request.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction how many clock cycles of read data it should expect.
The ALTMEMPHY megafunction uses the control_doing_rd signal to enable
its capture registers for the expected duration of the memory burst.
f
captures the read data from the memory.
resynchronizing it to the phy_clk domain by asserting the
control_rdata_valid signal when there is valid read data on the
control_rdata bus.
local_rdata_valid signal when there is valid read data on the local_rdata
bus. If Enable error correction and detection logic is disabled, there is no delay
between the control_rdata and the local_rdata buses. If there is ECC logic
in the controller, there is one or three clock cycles of delay between the
control_rdata and local_rdata buses.
Refer to the “Handshake Mechanism Between Read Commands and
Read Data” section of the
User Guide (ALTMEMPHY)
shows three consecutive read requests of the same burst
External Memory PHY Interface Megafunction
for more details of this interface.
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals
Related parts for IPR-SDRAM/HPDDR
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![IPR-SDRAM/DDR](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/DDR2](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/DDR2
Manufacturer:
Altera
Datasheet:
![IPR-SDRAM/HPDDR2](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SDRAM/HDDR2
Manufacturer:
Altera
Datasheet:
![IPR-RLDRAMII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDRAMII
Manufacturer:
Altera
Datasheet:
![IPR-HPMCII](/photos/24/19/241941/4696148_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-HPMCII
Manufacturer:
Altera
Datasheet:
![IPR-RLDII/UNI](/photos/24/19/241946/4696147_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-RLDII/UNI
Manufacturer:
Altera
Datasheet:
![IPR-SRAM/QDRII](/images/manufacturer_photos/0/0/40/altera_tmb.jpg)
Part Number:
Description:
IP CORE Renewal Of IP-SRAM/QDRII
Manufacturer:
Altera
Datasheet:
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet: