IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 60

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–32
Figure 4–12. Full Rate, Read-Write (Size 1), Read-Write (Size 2) Native Interface Mode
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Figure
control_dqs_burst[0]
control_wdata_valid
Mem Command (1)
control_doing_rd[0]
DDR Command (1)
control_rdata_valid
Controller-PHY Interface (Non-AFI)
local_rdata_valid
local_wdata_req
PHY Memory Interface
local_write_req
local_read_req
local_address
control_wdata
control_rdata
mem_dqs[0]
Local Interface
local_wdata
mem_dm[0]
ddr_cs_n[0]
local_ready
local_rdata
mem_addr
control_be
4–12:
local_size
mem_clk
mem_ba
mem_dq
phy_clk
cs_n[0]
ddr_ba
ddr_a
0 2 4
1
0000
0
2
AABB CCDD
000
8
[1]
RD
0
NOP
0000
[8]
[13]
RD NOP
EEFF
WR
4
FFFF
[20]
[4]
[9]
WR
NOP
0000
4
[5]
[21]
[12]
[2]
NOP
0000
RD
8
AABB
[3]
0000
NOP
[10]
WR
10
RD
8
0000
NOP
[16]
[11]
0000
NOP
[17]
[14]
WR
10
000000
[7]
00FF
0FF
[24]
[15]
0000
NOP
[22]
CCDD
3
1
[6]
0
Chapter 4: Functional Description
© March 2009 Altera Corporation
[23]
[19]
FFFF
[18]
FFFF
Interfaces and Signals