IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 38

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–10
DDR and DDR2 SDRAM High-Performance Controller User Guide
For partial writes, the ECC performs the following steps:
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The following corner cases can occur:
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Partial Bursts
Some DIMMs do not have the DM pins and so do not support partial bursts. A
minimum of four words must be written to the memory at the same time. In cases of
partial burst write, the ECC offers a mechanism similar to the partial write.
In cases of partial bursts, the write data from the native interface is stored in a 64-bit
wide FIFO buffer of maximum burst size depth, while in parallel a read command of
the corresponding addresses is sent to the DIMM. Further commands from the native
interface are stalled until the current burst is read, modified, and written back to the
memory controller.
ECC Latency
Using the ECC results in the following latency changes:
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Local Burst Length 1
For a local burst length of 1, the write latency increases by one clock cycle; the read
latency increases by one clock cycle (including checking and correction).
A partial write results in a read followed by write in the ECC controller, so latency
depends on the time the controller takes to fetch the data from the particular address.
Stalls further read or write commands from the Avalon-MM interface when it
receives a partial write condition.
Simultaneously sends a self-generated read command, for the partial write
address, to the memory controller.
Upon receiving a return data from the memory controller for the particular
address, the ECC decodes the data, checks for errors, and then sends it to the ECC
controller.
The ECC controller merges the corrected or correct dataword with the incoming
information.
Sends the updated dataword to the encoder for encoding and then sends to the
memory controller with a write command.
Releases the stall of commands from the Avalon-MM interface, which allows it to
receive new commands.
A single-bit error during the read phase of the read-modify-write process. In this
case, the single-bit error is corrected first, the single-bit error counter is
incremented and then a partial write is performed to this corrected decoded data
word.
A double-bit error during the read phase of the read-modify-write process. In this
case, the double-bit error counter is incremented and an interrupt is sent through
the Avalon-MM interface. The new write word is not written to its location. A
separate field in the interrupt status register highlights this condition.
Local Burst Length 1
Local Burst Length 2
Chapter 4: Functional Description
© March 2009 Altera Corporation
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