IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 53

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–9. Full Rate Read, Avalon-MM Interface Mode
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
Mem Command
Controller - PHY Interface (Non-AFI)
DDR Command
control_doing_read
control_rdata_valid
PHY - Memory Interface
Local Interface
local_rdata_valid
local_burstbegin
local_write_req
local_read_req
local_address
control_rdata
Figure
local_ready
local_rdata
mem_cs_n
mem_addr
local_size
mem_dqs
ddr_cs_n
mem_clk
mem_ba
mem_dq
phy_clk
ddr_ba
ddr_a
4–9:
(1)
(1)
Full Rate Read, Avalon-MM Interface Mode
Figure 4–9
mode, the controller allows you to use burst size 1 or 2. To achieve the highest
throughput, you bursts of 2, which correspond to a complete memory burst of 4.
Bursts of size 1 on the local interface are only half as efficient because each request still
corresponds to a memory burst of size 4 but only of half of the data is used.
The following sequence corresponds with the numbered items in
1. The user logic requests the first read by asserting the read request signal, the burst
00 02 04
begin signal, the burst size and address for this read. In this example, the request is
a burst of length 2 (4 on the memory side). The local_ready signal is asserted,
which indicates that the controller has accepted this request, and the user logic can
request another read or write in the following clock cycle. If the local_ready
signal was not asserted, the user logic must keep the read request, size, and
address signals asserted. The burst begin signal does not need to be held asserted
if the ready signal is not asserted.
f
2
[1] [2] [3]
NOP
shows three consecutive read requests of the same burst size. In full-rate
Refer to
RD
00
NOP
NOP
00
Avalon Interface Specifications
04 00 08
RD NOP RD
0
00
RD
[4] [5]
NOP
00
04
RD NOP RD
0
NOP
00 08
A
A
B
B
DDR and DDR2 SDRAM High-Performance Controller User Guide
C
NOP
[6]
C
D
D
E E
F
for more details.
F
AA BB
AA BB
Figure
CC DD EE
CC DD EE
[8]
4–9.
[7]
FF
FF
4–25