IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 44

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–16
DDR and DDR2 SDRAM High-Performance Controller User Guide
The following sequence corresponds with the numbered items in
page
1. The user logic requests the first write, by asserting the local_write_req signal,
2. The user logic requests a second write to a sequential address of size 2 (4 on the
3. The user logic requests a third write to a sequential address, again of size 2. The
4. The controller issues the necessary memory command and address signals to the
5. The controller asserts the control_wdata_valid signal to indicate to the
6. The controller asserts the control_dqs_burst signals to control the timing of
7. The ALTMEMPHY megafunction issues the write command and sends the write
local_wdata =
local_be =
mem_dq
mem_dm
and the size and address for this write. In this example, the request is a burst of
length 2 (4 on the memory side) to chip select 1. The local_ready signal is
asserted, which indicates that the controller has accepted this request, and the user
logic can request another read or write in the following clock cycle. If the
local_ready signal was not asserted, the user logic must keep the write request,
size, and address signals asserted until the local_ready signal is registered
high.
f
1
To map local_wdata and local_be to mem_dq and mem_dm, consider the
following full rate example with 32-bit wide local_wdata and 16-bit wide
mem_dq.
These values map to:
memory side). The local_ready signal remains asserted, which indicates that
the controller has accepted the request. The address increments by the local burst
size.
controller is able to buffer up to four requests so the local_ready signal stays
high and the request is accepted.
ALTMEMPHY megafunction for it to send to the memory device.
ALTMEMPHY megafunction that valid write data and write data masks are
present on the inputs to the ALTMEMPHY megafunction.
the DQS signal that the ALTMEMPHY megafunction issues to the memory.
f
data and write DQS to the memory.
4–15.
=
=
local_be is active high while mem_dm is active low.
Refer to
Refer to the “Handshake Mechanism Between Write Commands and
Write Data” section of the
User Guide (ALTMEMPHY)
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Avalon Interface Specifications
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External Memory PHY Interface Megafunction
for more details of this interface.
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for more details.
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Chapter 4: Functional Description
© March 2009 Altera Corporation
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Figure 4–5 on
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Interfaces and Signals
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