IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 40

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–12
Table 4–4. Example Design and Testbench Files
Example Driver
DDR and DDR2 SDRAM High-Performance Controller User Guide
<variation name>_example_top_tb.v or .vhd
<variation name>_example_top.v or .vhd
<variation name>_mem_model.v or .vhd
<variation name>_example_driver.v or .vhd
<variation name> .v or .vhd
<variation name>.qip
1
Table 4–4
testbench.
There are two Altera-generated memory models available—associative-array memory
model and full-array memory model.
The associative-array memory model (<variation name>_mem model.v) allocates
reduced set of memory addresses with a default depth of 2,048 or 2K address spaces.
This allocation allows for a larger memory array compilation and simulation which
enables you to easily reconfigure the depth of the associate array.
The full-array memory model (<variation name>_mem model_full.v) allocates
memory for all addresses accessible by the DDR cores. This allocation makes it
impossible to simulate large memory (more than 2K address spaces) designs, because
simulators need more memory than what is available on a typical system.
The memory model, <variation name>_test_component.v/vhd, used in SOPC Builder
designs, is actually a variation of the full-array memory model. To ensure your
simulation works in SOPC Builder, use memory model with less than 512-Mbit
capacity.
The example driver is a self-checking test pattern generator for the memory interface.
It uses a state machine to write and read from the memory to verify that the interface
is operating correctly.
It performs the following tests and loops back the tests indefinitely:
■
Filename
Sequential addressing writes and reads
The state machine writes pseudo-random data generated by a linear feedback shift
register (LFSR) to a set of incrementing row, bank, and column addresses. The
state machine then resets the LFSR, reads back the same set of addresses, and
compares the data it receives against the expected data. You can adjust the length
and pattern of the bursts that are written by changing the MAX_ROW, MAX_BANK,
and MAX_COL constants in the example driver source code, and the entire memory
space can be tested by adjusting these values. You can skip this test by setting the
test_seq_addr_on signal to logic zero.
describes the files that are associated with the example design and the
Testbench for the example design.
Example design.
Memory model.
Example driver.
Top-level description of the custom MegaCore function.
Contains Quartus II project information for your MegaCore
function variations.
Description
Chapter 4: Functional Description
© March 2009 Altera Corporation
Example Design