IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 55

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Interfaces and Signals
Figure 4–10. Half Rate Read, Native Interface Mode
Note to
(1) DDR Command and Mem Command show the command that the command signals are issuing.
© March 2009 Altera Corporation
DDR Command
control_doing_read
Mem Command
control_rdata_valid
Controller - PHY Interface (Non-AFI)
local_rdata_valid
local_write_req
local_read_req
PHY Memory Interface
local_address
control_rdata
local_ready
Figure
local_rdata
mem_cs_n
mem_addr
local_size
mem_dqs
ddr_cs_n
mem_clk
mem_ba
mem_dq
Local Interface
phy_clk
ddr_ba
ddr_a
4–10:
(1)
(1)
00
Half Rate Read, Native Interface Mode
Figure 4–10 on page 4–27
size. In half-rate mode, the controller allows you to use burst size 1, which
corresponds to a complete memory burst of 4.
The following sequence corresponds with the numbered items in
1. The user logic requests the first read by asserting the read request signal, the burst
2. The user logic requests a second read to a different address, again of size 1 (4 on
1
[1]
01
size and address for this read. In this example, the request is a burst of length 1 (4
on the memory side). The local_ready signal is asserted, which indicates that
the controller has accepted this request, and the user logic can request another
read or write in the following clock cycle. If the local_ready signal was not
asserted, the user logic must keep the read request, size, and address signals
asserted.
the memory side). The controller is able to buffer up to four requests so the
local_ready signal stays high and the request is accepted.
02
[2]
[3]
NOP
shows three consecutive read requests of the same burst
00
RD
04
0
NOP
08
[4] [5]
DDR and DDR2 SDRAM High-Performance Controller User Guide
00
NOP
RD
04
0
08
A A B B C C
NOP
D
D
E E F F
[6]
Figure
BBAA DDCC FFEE
BBAA DDCC FFEE
4–10.
[8]
4–27
[7]