IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 10

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–6
Table 1–7. Resource Utilization in Stratix III Devices
Table 1–8. Resource Utilization in Stratix IV Devices
DDR and DDR2 SDRAM High-Performance Controller User Guide
Controller Rate
Controller Rate
Half
Full
Half
Full
Width (Bits)
Width (Bits)
Local Data
Local Data
Table 1–7
controller in AFI mode (including ALTMEMPHY) for Stratix III devices.
Table 1–8
controller in AFI mode (including ALTMEMPHY) for Stratix IV devices.
256
288
256
288
256
288
256
288
32
64
32
64
32
64
32
64
shows typical sizes for the DDR or DDR2 SDRAM high-performance
shows typical sizes for the DDR or DDR2 SDRAM high-performance
Memory Width
Memory Width
(Bits)
(Bits)
16
64
72
16
64
72
16
64
72
16
64
72
8
8
8
8
Combinational
Combinational
ALUTs
ALUTs
1,755
1,820
2,202
2,289
1,631
1,630
1,743
1,752
1,824
2,210
2,321
1,622
1,630
1,749
1731
1736
Dedicated Logic
Dedicated Logic
Registers
Chapter 1: About These MegaCore Functions
Registers
1,452
1,597
2,457
2,601
1,369
1,448
1,906
1,983
1,432
1,581
2,465
2,613
1,351
1,431
1,897
1,975
Performance and Resource Utilization
© March 2009 Altera Corporation
Memory
Memory
(M9K)
(M9K)
10
2
3
9
2
2
5
6
1
2
8
9
1
1
4
5