IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 42

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–14
Interfaces and Signals
Interface Description
DDR and DDR2 SDRAM High-Performance Controller User Guide
This section describes the following topics:
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This section describes the following local-side interface requests. You can use the half-
rate and full-rate modes with both Avalon-MM and native interface modes.
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Full Rate Write, Avalon-MM Interface Mode
Figure 4–5 on page 4–15
using the Local Interface Protocol option set to Avalon Memory-Mapped interface.
The figure shows three back-to-back write requests, each of burst size 2 to sequential
addresses. In full-rate mode, the controller allows you to use burst size 1 or 2. To
achieve the highest throughput, you should use bursts of size 2, which correspond to
a complete memory burst of 4. Bursts of size 1 on the local interface are only half as
efficient because each request still corresponds to a memory burst of size 4 but only of
half of the data is used.
“Interface Description”
“Signals” on page 4–37
“Full Rate Write, Avalon-MM Interface Mode” on page 4–14
“Full Rate Write, Native Interface Mode—Non-Consecutive Write” on page 4–17
“Half Rate Write, Avalon-MM Interface Mode” on page 4–20
“Half Rate Write, Native Interface Mode” on page 4–22
“Full Rate Read, Avalon-MM Interface Mode” on page 4–25
“Half Rate Read, Native Interface Mode” on page 4–27
“Half Rate Read, Avalon-MM Interface Mode—Non-Consecutive Read” on
page 4–28
“Full Rate, Native Interface Mode—Alternate Read-Write” on page 4–31
“User Refresh Control” on page 4–34
“Self-Refresh and Power-Down Commands” on page 4–35
“Auto-Precharge Commands” on page 4–36
shows write accesses with a controller in full-rate mode and
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals