IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 70

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–42
Table 4–7. Local Interface Signals (Part 4 of 4)
Table 4–8. DDR and DDR2 SDRAM Interface Signals (Part 1 of 2)
DDR and DDR2 SDRAM High-Performance Controller User Guide
local_powerdn_req
local_powerdn_ack
local_self_rfsh_req
local_self_rfsh_ack
mem_dq[]
mem_dqs[]
mem_clk
mem_clk_n
mem_a[]
mem_ba[]
mem_cas_n
mem_cke[]
mem_cs_n[]
mem_dm[]
mem_odt[]
mem_ras_n
Signal Name
Signal Name
(1)
(1)
Table 4–8
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Direction
Output
Output
Input
Input
shows the DDR and DDR2 SDRAM interface signals.
Memory data bus. This bus is half the width of the local read and write data
busses.
Memory data strobe signal, which writes data into the DDR or DDR2 SDRAM and
captures read data into the Altera device.
Clock for the memory device.
Inverted clock for the memory device.
Memory address bus.
Memory bank address bus.
Memory column address strobe signal.
Memory clock enable signals.
Memory chip select signals.
Memory data mask signal, which masks individual bytes during writes.
Memory on-die termination control signal (DDR2 SDRAM only).
Memory row address strobe signal.
User control of the power down feature. If Enable power down controls option
is enabled, you can request that the controller place the memory devices into a
power-down state as soon as it can without violating the relevant timing
parameters and responds by asserting the local_powerdn_ack signal.
You can hold the memory in the power-down state by keeping this signal
asserted. The controller brings the memory out of the power-down state to
issue periodic auto-refresh commands to the memory at the appropriate
interval if you hold it in the power-down state. You can release the memory
from the power-down state at any time by deasserting the
local_powerdn_ack signal once it has successfully brought the memory
out of the power-down state.
Power-down request acknowledge signal. This signal is asserted and
deasserted in response to the local_powerdn_req signal from the user.
is enabled, you can request that the controller place the memory devices into a
self-refresh state by asserting this signal. The controller places the memory in
the self-refresh state as soon as it can without violating the relevant timing
parameters and responds by asserting the local_self_rfsh_ack
signal. You can hold the memory in the self-refresh state by keeping this signal
asserted. You can release the memory from the self-refresh state at any time
by deasserting the local_self_rfsh_req signal and the controller
responds by deasserting the local__self_rfsh_ack signal once it has
successfully brought the memory out of the self-refresh state.
Self refresh request acknowledge signal. This signal is asserted and
deasserted in response to the local_self_rfsh_req signal from the
user.
User control of the self-refresh feature. If Enable self-refresh controls option
Description
Description
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals