IPR-CIC Altera, IPR-CIC Datasheet - Page 7

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function
General Description
General Description
MegaCore Verification
Performance and Resource Utilization
© December 2010 Altera Corporation
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CIC filters (also known as Hogenauer filters) are computationally efficient for
extracting baseband signals from narrow-band sources using decimation, and for
constructing narrow-band signals from processed baseband signals using
interpolation.
CIC filters use only adders and registers, and require no multipliers to handle large
rate changes. Therefore, CIC is a suitable and economical filter architecture for
hardware implementation, and is widely used in sample rate conversion designs such
as digital down converters (DDC) and digital up converters (DUC).
For a more detailed description, refer to
page
Before releasing a version of the CIC MegaCore function, Altera runs comprehensive
regression tests to verify its quality and correctness.
Custom variations of the CIC MegaCore function are generated to exercise its various
parameter options, and the resulting simulation models are thoroughly simulated
with the results verified against master simulation models.
This section shows typical expected performance for a CIC MegaCore function using
the Quartus II software, version 8.0 with Cyclone III, and Stratix IV devices.
The following general settings apply to all parameterizations:
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Optimization for speed by specifying the number of pipeline stages used by each
integrator.
Compensation filter coefficients generation.
Easy-to-use MegaWizard™ interface for parameterization and hardware
generation.
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators.
DSP Builder ready.
Number of stages: 5
Rate change factor: 8
Differential delay: 1
Integrator data storage: Memory (whenever possible)
Differentiator data storage: Memory (whenever possible)
Input data width: 16
Output data width: 16 (unless specified otherwise in table)
Output rounding: Truncation
4–1.
“Cascaded Integrator Comb Filters” on
CIC MegaCore Function User Guide
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