IPR-CIC Altera, IPR-CIC Datasheet - Page 17

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Table 2–1. Generated Files
Simulate the Design
© December 2010 Altera Corporation
<variation name>_tb.vhd, or .v
Notes to
(1) The <variation name> prefix is added automatically using the base output file name you specified in the MegaWizard Plug-In Manager.
(2) The <entity name> prefix is added automatically. The VHDL code for each MegaCore instance is generated dynamically when you click Finish
(3) The .cmp, _bb.v and .html files are only generated when enabled in the Summary page of the MegaWizard interface.
(4) The _syn.vhd or _syn.v file is only generated when enabled in the EDA page of the MegaWizard interface.
so that the <entity name> is different for every instance. It is generated from the <variation name> by appending _cic.
Table
f
2–1:
Filename
1
A MegaCore function report file containing a list of the design files and ports defined
for your MegaCore function variation is saved as a HTML file if you turn on the
MegaCore function report file check box in the MegaWizard Summary page.
For a full description of the signals supported on external ports for your MegaCore
function variation, refer to
You can simulate your design using the MegaWizard-generated VHDL or Verilog
HDL IP functional simulation models and testbench.
The IP functional simulation model is either a .vo or .vho file, depending on the
output language you specified. Compile the .vo or .vho file in your simulation
environment to perform functional simulation of your custom variation of the
MegaCore function.
For more information about IP functional simulation models, refer to the
Altera Designs
Simulating in Third-Party Simulation Tools Using NativeLink
You can perform a simulation in a third-party simulation tool from within the
Quartus II software, using NativeLink.
The Tcl script file <variation name>_nativelink.tcl can be used to assign default
NativeLink testbench settings to the Quartus II project.
To perform a simulation in the Quartus II software using NativeLink, perform the
following steps:
1. Create a custom MegaCore function variation as described earlier in this chapter
2. Verify that the absolute path to your third-party EDA tool is set in the Options
3. On the Processing menu, point to Start and click Start Analysis & Elaboration.
4. On the Tools menu, click Tcl scripts. In the Tcl Scripts dialog box, select the
but ensure you specify your variation name to match the Quartus II project name.
page under the Tools menu in the Quartus II software.
<variation name>_nativelink.tcl Tcl script and click Run. Check for a message
confirming that the Tcl script was successfully loaded.
(Note 1)
&
chapter in volume 3 of the Quartus II Handbook.
A VHDL or Verilog HDL testbench file for the CIC MegaCore function variation. The
VHDL file is generated when a VHDL top level has been chosen or the Verilog HDL
file when a Verilog HDL top level has been chosen.
(Note 2)
Table 4–3 on page
Description
4–12.
CIC MegaCore Function User Guide
Simulating
2–7