IPR-CIC Altera, IPR-CIC Datasheet - Page 18

IP CORE Renewal Of IP-CIC

IPR-CIC

Manufacturer Part Number
IPR-CIC
Description
IP CORE Renewal Of IP-CIC
Manufacturer
Altera
Datasheet

Specifications of IPR-CIC

Software Application
IP CORE, DSP Filters And Transforms
Supported Families
Arria GX, Cyclone, HardCopy, Stratix, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
2–8
Compile the Design and Program a Device
CIC MegaCore Function User Guide
f
f
5. On the Assignments menu, click Settings, expand EDA Tool Settings, and select
6. On the Tools menu, point to EDA Simulation Tool and click Run EDA RTL
For more information, refer to the
Quartus II Handbook.
You can use the Quartus II software to compile your design. After a successful
compilation, you can program the targeted Altera device and verify the design in
hardware.
For instructions on compiling and programming your design, and more information
about the MegaWizard Plug-In Manager flow, refer to the Quartus II Help.
Simulation. Select a simulator under Tool name then in NativeLink Settings,
select Compile test bench and click Test Benches.
Simulation.
The Quartus II software selects the simulator, and compiles the Altera libraries,
design files, and testbenches. The testbench runs and the waveform window
shows the design signals for analysis.
Simulating Altera Designs
© December 2010 Altera Corporation
chapter in volume 3 of the
MegaWizard Plug-In Manager Flow
Chapter 2: Getting Started

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