IPR-CIC Altera, IPR-CIC Datasheet - Page 27

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Cascaded Integrator Comb Filters
Data Storage
Output Options
© December 2010 Altera Corporation
f
Data storage in the integrators and differentiators can utilize either logic cells, or
memory blocks. The type of data storage can be selected in the MegaWizard interface
when the data storage options are enabled. The memory types are then selected
automatically by the Quartus II software depending on the chosen device.
For information about when the memory option is enabled, refer to
page
You can select output options for the output data bit width and rounding options.
Output Data Width
For a decimation filter, the gain at the output of the filter is:
Therefore, the data width at the output stage for if full resolution is:
If you have selected an output data width that is smaller than the full output
resolution data width, the Hogenauer pruning technique can be applied to reduce the
data widths across the filter stages and hence the overall resource utilization.
For an interpolation filter, the gain at each filter stage is:
Hence the required data width at the ith stage is:
and the data width at the output stage is:
When the differential delay is one, the bit width at each integrator stage is increased
by one to ensure stability.
For more information about these calculations, refer to Hogenauer, Eugene. An
Economical Class of Digital Filters For Decimation and Interpolation, IEEE Transactions on
Acoustics, Speech and Signal Processing, Vol. ASSP-29, pp. 155-162, April 1981.
where Bin is the input data width.
1
where Bin is the input data width.
3–4.
A data width of Bout is required for each integrator and differentiator for no
data loss.
G
i
B
=
out







2
2
------------------------------------- -
B
=
i
2N 1
out
W
–
B
i
=
in
(
=
R
RM
+
G
B
Nlog
B
=
in
)
in
i N
–
+
(
+
RM
2
Nlog
log
(
RM
i
i
)
N
=
=
2
2
( )
) log
(
G
N
RM
1 2 … N
–
i
, ,
+
)
1 … 2N
,
2
R ( )
,
,
CIC MegaCore Function User Guide
Table 3–3 on
4–3