IPR-CIC Altera, IPR-CIC Datasheet - Page 35

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Avalon Streaming Interface
Avalon-ST Interface Data Transfer Timing
Figure 4–11. Avalon-ST Interface Timing with READY_LATENCY=0
Figure 4–12. Packet Data Transfer
© December 2010 Altera Corporation
startofpacket
channel[1:0]
endofpacket
data[31:24]
data[23:16]
data[15:8]
ready
error
error[1:0]
valid
data[7:0]
data
clk
ready
valid
clk
Figure 4–11
The source provides data and asserts valid on cycle 1, even though the sink is not
ready. The source waits until cycle 2, when the sink does assert ready, before moving
onto the next data cycle. In cycle 3, the source drives data on the same cycle and
because the sink is ready to receive it, the transfer occurs immediately. In cycle 4, the
sink asserts ready, but the source does not drive valid data.
Packet Data Transfers
A beat is defined as the transfer of one unit of data between a source and sink
interface. This unit of data may consist of one or more symbols and makes it is
possible to support modules that convey more than one piece of information about
each valid cycle.
Packet data transfers are used for multichannel transfers. Two additional signals
(startofpacket and endofpacket) are defined to implement the packet transfer.
Figure 4–12
multiple symbols per beat scenario applies to both the sink interface on MISO CIC
filters and the source interface of SIMO CIC filters. All other interfaces operate with a
single symbol per beat, but the interfaces also support multiple channels using
packets.
The data transfer in
valid are asserted.
0
1
1
illustrates the data transfer timing.
shows an example where four symbols are transferred on each beat. This
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o
Figure 4–12
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occurs on cycles 1, 2, 4, and 5, when both ready and
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CIC MegaCore Function User Guide
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4–11