IPR-CIC Altera, IPR-CIC Datasheet - Page 16

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–6
Generated Files
Table 2–1. Generated Files
CIC MegaCore Function User Guide
<entity name>.ocp
<entity name>.vhd or .v
<variation name>.bsf
<variation name>.cmp
<variation name>.html
<variation name>.qip
<variation name>.log
<variation name>.vhd or .v
<variation name>.vho or .vo
<variation name>_bb.v
<variation name>_fir_comp_coeff.m
<variation name>_syn.vhd or _syn.v
<variation name>_nativelink.tcl
<variation name>_quartus.tcl
<variation name>_tb_input.txt
f
Filename
13. Click Exit to close the progress report window. Then click Yes on the Quartus II IP
Refer to the Quartus II Help for more information about the MegaWizard Plug-In
Manager.
Table 2–1
directory.
The names and types of files vary depending on the variation name and HDL type
you specify during parameterization For example, a different set of files are created
based on whether you create your design in Verilog HDL or VHDL.
Files prompt to add the .qip file describing your custom MegaCore function
variation to the current Quartus II project.
(Note 1)
describes the generated files and other files that may be in your project
&
Encrypted OpenCore Plus file.
A VHDL or Verilog HDL file that defines the design entity.
Quartus II block symbol file for the MegaCore function variation. You can use this
file in the Quartus II block diagram editor.
A VHDL component declaration file for the MegaCore function variation. Add the
contents of this file to any VHDL architecture that instantiates the MegaCore
function.(3)
MegaCore function report file in hypertext markup language format which contains
lists of the generated files and ports for the MegaCore function
A single Quartus II IP file is generated that contains all of the assignments and other
information required to process your MegaCore function variation in the Quartus II
compiler. You are prompted to add this file to the current Quartus II project when
you exit from the MegaWizard.
Log file.
A VHDL or Verilog HDL file that defines a VHDL or Verilog HDL top-level description
of the custom MegaCore function variation. Instantiate the entity defined by this file
inside of your design. Include this file when compiling your design in the Quartus II
software.
A VHDL or Verilog HDL output file that defines the IP functional simulation model.
Verilog HDL black-box file for the MegaCore function variation. Use this file when
using a third-party EDA tool to synthesize your
A MATLAB script for generating compensation FIR filter coefficients.
A timing and resource estimation netlist for use in some third-party synthesis
tools.(4)
A Tcl script that can be used to assign NativeLink simulation testbench settings to
the Quartus II project.
A Tcl script that can be used to run compilation in the Quartus II software.
A text file containing input data for the testbench.
(Note 2)
Description
design.(3)
© December 2010 Altera Corporation
MegaWizard Plug-In Manager Flow
Chapter 2: Getting Started
variation.(3)