IPR-CIC Altera, IPR-CIC Datasheet - Page 29

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 4: Functional Description
Cascaded Integrator Comb Filters
Figure 4–6. Multiple Input Single Output Architecture
© December 2010 Altera Corporation
(B, D)
(A, C)
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This combined filter uses fewer resources than using many individual CIC filters. For
example, a two-channel parallel filter requires two clock cycles to calculate two
outputs. The resulting hardware would need to run at twice the data rate of an
individual filter. This is especially useful for higher rate changes where adders grow
particularly large.
To minimize the number of logic elements, a multiple input single output (MISO)
architecture can be used for decimation filters, and a single input multiple output
(SIMO) architecture for interpolation filters as described in the following sections.
Multiple Input Single Output (MISO)
In many practical designs, channel signals come from different input interfaces. On
each input interface, the same parameters including rate change factors are applied to
the channel data that the CIC filter is going to process. The CIC MegaCore function
allows the flexibility to exploit time sharing of the low rate differentiator sections.
This is achieved by providing multiple input interfaces and processing chains for the
high rate portions, then combining all of the processing associated with the lower rate
portions into a single processing chain. This strategy can lead to full utilization of the
resources and represents the most efficient hardware implementation. These
architectures are known as multiple input single output (MISO) decimation filters.
Figure 4–6
total of four channels. In this example, the symbols A, B, C, D are multiplexed into one
output A, B, C, D.
The sampling frequency of the input data is such that it is only possible to time
multiplex two channels per bus, therefore the CIC filter must be configured with two
input interfaces. Because two interfaces are required, the rate change factor must also
be at least two to exploit this architecture. Up to 1,024 channels can be supported by
using multiple input interfaces in this way.
MISO architecture is applied when a decimation filter type is chosen and the number
of interfaces selected in the MegaWizard interface is greater than one.
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shows an example of the MISO architecture for a CIC filter that processes a
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CIC MegaCore Function User Guide
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(A, B, C, D)
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