IPR-CIC Altera, IPR-CIC Datasheet - Page 23

• Manufacturer Part Number: IPR-CIC
• Description: IP CORE Renewal Of IP-CIC
• Manufacturer: Altera

Specifications of IPR-CIC

• Software Application: IP CORE, DSP Filters And Transforms
• Supported Families: Arria GX, Cyclone, HardCopy, Stratix, Stratix II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 3: Parameter Settings
Parameter Descriptions
Table 3–3. CIC MegaCore Function Architecture Page (Part 2 of 2)
Table 3–4. CIC MegaCore Function Input/Output Options Page Parameters
© December 2010 Altera Corporation
Use pipelined integrators
Number of pipeline stages
per integrator
Notes to
(1) The product of the Number of interfaces and the Number of channels per interface must be no more than 1024.
(2) The Memory option is available for integrator data storage when the Number of channels per interface is greater than 4.
(3) The Memory option is available for differentiator data storage when the product of the Differential delay, Number of channels per interface
(4) The options available depend on the target device family. When AUTO is selected, the Quartus II software automatically selects the optimum
Input data width
Full output resolution
Output data width
Output Rounding Options
Apply Hogenauer pruning
across filter stages
Note for
(1) Refer to
and Number of interfaces is greater than 4.
RAM type for the currently selected device family.
Parameter
Parameter
Table
Table
“Output Rounding” on page 4–4
3–4:
3–3:
Table 3–4
1–32
On, Off
1 to calculated
maximum data width
Truncation,
Convergent rounding,
Rounding up,
Saturation
On, Off
On or Off
1–4
shows the parameters that can be set in the Input/Output Options page.
Value
Value
for more information about these options.
Specifies the input data width in bits.
Turn on to enable full output resolution. When selected, the output
data width is set to its maximum and the output rounding options are
disabled.
Specifies the output data width in bits.
Select the required rounding output mode. Note that the saturation
limit is the maximum value for overflow or the minimum value for
negative overflow.
This option is available only when a Decimator filter type is selected in
the Architecture page. Turn on if you want to apply Hogenauer
pruning across the filter stages.
Turn on to use pipelined integrators. This option is available when
the Number of channels per interface is greater than or equal to 2
(or greater than or equal to 6, when the Memory option is selected
for integrator data storage).
Use this option for multichannel designs that have large input bit
width and require high f
designs targeting Stratix family devices, but not for Cyclone family
devices.
Specifies the number of pipeline stages used by each integrator.
Adding additional integrators can improve f
resource utilization.
The maximum number of pipeline stages, that can be used, is
dependent on the number of channels and whether Memory or
Logic Cells is selected for integrator data storage. When Memory
is selected, the maximum number of pipeline stages equals the
number of channels minus 5. When Logic Cells is selected, the
maximum number of pipeline stages equals the number of
channels.
(1)
MAX
Description
. This option is recommended for
Description
CIC MegaCore Function User Guide
MAX
but increases the
3–5