IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 85

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Clocks and Reset
3.8.3. MAC XGMII Clocks
Figure 3–33. MAC XGMII Clocks
3.8.4. Clock Signals
Table 3–57. Clock Signals (Part 1 of 2)
© July 2010 Altera Corporation
sysclk
sysclk_90
Signal
avl_st_tx_clk
Avalon-ST Tx IF
Avalon-ST Rx IF
sysclk
sysclk_90
avalon addr & data
avalon_clk
In this configuration the application logic provides the system clock for the MAC,
MAC side of the FIFO logic, and the XGMII transmit data and clock interface as
Figure 3–33
Table 3–57
configurations.
Avalon-ST clock domain (avl_st_tx_clk)
Avalon-MM clock domain (avalon_clk)
Sysclk domain (sysclk)
156.25 MHz system clock for the state machines and datapath. Can be shared with other 10 Gbps
Ethernet IP cores in the same device. You must provide this clock.
The sysclk phase-shifted by 90 degrees. This clock ensures that the transmitter clock and the
Tx data are 90 degrees apart in an XGMII interface. In your design, this clock must be derived from
the sysclk or form the same source as sysclk.
Altera FPGA
FIFO
FIFO
Wr
Wr
describes the signals that comprise the clock interface for the various
Interface
Avalon
illustrates.
FIFO
FIFO
Rd
Rd
MAC Tx
MAC Rx
Sync
Description
64-bit SDR
XGMII IF
10-Gbps Ethernet IP Functional Description
Dynamic register bits (sysclk)
PHY
Static register bits
32-bit DDR
XGMII IF
xgmii_tx_clk
xgmii_rx_clk
3–59