IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 15

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started with the 10-Gbps Ethernet IP
Design Flows
2.3.1. MegaWizard Plug-in Manager Design Flow
2.3.2. SOPC Builder Design Flow
© July 2010 Altera Corporation
1
To customize you 10-Gbps Ethernet design using the MegaWizard Plug-In Manager
design flow, complete the following steps.
1. Open your Quartus II project file, tge_91.qpf.
2. Launch the MegaWizard Plug-in Manager from the Tools menu, and follow the
3. Specify the parameters on the Parameter Settings tab.
4. On the EDA tab, turn on Generate simulation model to generate an IP functional
5. On the Summary tab, select the files you want to generate. A grey checkmark
6. Click Finish to generate the IP core and supporting files.
The MegaWizard generates a sample testbench, RTL files, SDC timing constraints,
and placement and routing constraints. Their usage is explained in the following
sections.
In SOPC Builder you add the IP core directly to a new or existing SOPC Builder
system. If your system includes other SOPC Builder components, such as the Nios II
processor, external memory controllers, or scatter-gather DMA controllers, you can
quickly create an SOPC Builder system with an Ethernet interface.
2.3.2.1. Specify Parameters
Follow the steps below to specify 10-Gbps Ethernet parameters using the SOPC
Builder flow.
prompts in the MegaWizard Plug-In Manager interface to create a custom
megafunction variation. (The name you choose for your variation must not start
with a number and should different from component names in the 10-Gbps
Ethernet library that you installed.)
For detailed explanation of the parameters, refer to
on page
simulation model for the IP core in the selected language.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
1
c
indicates a file that is automatically generated. All other files are optional.
You can now integrate the 10-Gbps Ethernet variant generated by the MegaWizard
into your system design with other custom logic.
Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a non-functional
design.
Some third-party synthesis tools can use a netlist that contains only the
structure of the IP core, but not detailed logic, to optimize performance of
the design that contains the IP core. If your synthesis tool supports this
feature, turn on Generate netlist.
2–4.
Getting Started with the 10-Gbps Ethernet IP
“IP Core Parameterization”
2–9