IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 22

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–16
Example 2–1. Transcript from Successful Run in ModelSim
# DESC: Demonstration testbench
# ***********************************************************
Time: 45 ns
# 160005 Info: Avalon MM write at addr_hex=c, data_hex=34221400,
# 180005 Info: Avalon MM write at addr_hex=10, data_hex=80007bab,
# 200005 Info: Avalon MM write at addr_hex=300, data_hex=fe453681,
# 220005 Info: Avalon MM write at addr_hex=304, data_hex=8000c43c,
# 240005 Info: Avalon MM write at addr_hex=5c, data_hex=c,
# 260005 Info: Avalon MM write at addr_hex=1c, data_hex=3c0,
# 280005 Info: Avalon MM write at addr_hex=20, data_hex=40,
# 300005 Info: Avalon MM write at addr_hex=24, data_hex=3c0,
# 320005 Info: Avalon MM write at addr_hex=28, data_hex=40,
# 340005 Info: Avalon MM write at addr_hex=2c, data_hex=3c0,
# 360005 Info: Avalon MM write at addr_hex=30, data_hex=40,
# 380005 Info: Avalon MM write at addr_hex=34, data_hex=3c0,
# 400005 Info: Avalon MM write at addr_hex=38, data_hex=40,
# 420005 Info: Avalon MM write at addr_hex=8, data_hex=80000203,
# 742759 eth_gen generating packet pkt_type
# 851559 eth_gen generating packet pkt_type
# 963559 eth_gen generating packet pkt_type
# 1327247 avl_st_checker : received packet
# 1423247 avl_st_checker : received packet
# 1538447 avl_st_checker : received packet
Getting Started with the 10-Gbps Ethernet IP
Instance: tb.DUT.nl1ii0ii.pll2
2.4.3.1. Typical Test Sequence
A typical test case performs the following operations after a simulated power-on
reset:
1. Initialize the 10-Gbps Ethernet IP core, which consists the following operations:
2. Start transmission and clear the Rx and Tx FIFOs.
2.4.3.2. Running sample test case
Before you can run the example tests, you must compile several RTL files and
libraries. A script in the /tb directory performs these tasks. To run the script, complete
the following tasks:
1. Change to the <project_dir>/tge_91/tb/verilog directory.
2. Launch ModelSim software.
3. Type the following command at the command prompt:
4. Upon successful completion, the following text appears in the ModelSim
a. Set the operation mode in the command_config register.
b. Set the address via the mac_0 and mac_1 registers.
c. Set the IPG for transmit frames via the tx_ipg_length register.
d. Set the Avalon-ST FIFO threshold registers.
e. Set the supplemental unicast addresses.
source demo_run_modelsim.tcl r
transcript:
100 -- pkt_size
101 -- pkt_size
102 -- pkt_size
Chapter 2: Getting Started with the 10-Gbps Ethernet IP
time=240005
time=280005
time=320005
time=360005
time=400005
time=260005
time=300005
time=340005
time=380005
time=160005
time=420005
time=180005
© July 2010 Altera Corporation
time=200005
time=220005
100
101
102
Functional Verification