IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 39

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Table 3–5. Tx XGMII SDR interface
© July 2010 Altera Corporation
rs_tx_data[63:0]
rs_tx_ctrl[7:0]
Signal Name
Figure 3–12
Figure 3–12. SDR XGMII Interface
Note to
(1) The SDR interface is synchronous to the Tx PHY clock.
Table 3–5
3.2.3.3. Error Conditions on Tx Datapath
During frame transmission, if an error condition is detected, the MAC sends|E|
control characters on the data lanes to signal an error to the PHY. The MAC restarts
the frame when the client sends a new frame with a start of frame indication.
The only error condition defined for the Tx datapath is FIFO underflow. (The FIFO
can be read when it does not have data, which may occur when the MAC tries to
prefetch data.) However, an error occurs if the FIFO deasserts the valid signal before
the end of a packet. In this case, the MAC suffers from data starvation; there is no
buffer in the MAC to compensate. Because the IEEE 802.3 standard requires continuos
transmission, the packet is terminated with an |E|. The remainder of the packet is
read when available and data is ignored, until the next start of packet.
3.2.3.4. Order of Transmission
Bytes are transmitted starting with the preamble and ending with the FCS in
accordance with the IEEE 802.3 standard. All individual header bytes are transmitted
LSB first except the length/type, VLAN tag, VLAN info, and pause quanta, which are
transmitted MSB first. The data bus is 64-bits wide; the first byte of the destination
address is carried on bits [63:56]. The FCS is transmitted with the CRC[32] bit first.
The address arrives in the same order as it was received. The client side of Tx interface
bus is big endian.
Dir
Figure
O
O
describes the signals that comprise the SDR XGMII Tx interface.
8-lane data bus carrying bytes[7:0] of the MAC Tx module
8-bit signal where each bit indicates when a control octet is present on the
corresponding rs_tx_data byte lane.
3–12:
illustrates the SDR XGMII interface for the Tx datapath.
Arria II GX, Stratix II GX, Stratix IV GX, or HardCopy IV Device
Table 3–6
MAC Tx
shows the fields of a Tx packet.
rs_tx_data[63:0]
rs_tx_ctrl[7:0]
Description
(internal ALT2GX
Altera PHY
10-Gbps Ethernet IP Functional Description
transceiver)
or ALTGX
3–13