IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 79

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Register Descriptions
Table 3–55. MDIO Frame Field Descriptions—Clause 45
© July 2010 Altera Corporation
PRE
ST
OP
PRTAD
DEVAD
TA
Address/
Data
Idle
Name
Preamble. 32 bits of logical 1 sent prior to every transaction.
The start of frame for indirect access cycles is indicated by the <00> pattern. This pattern assures a transition
from the default one and identifies the frame as an indirect access. Frames that contain the ST=01 pattern
defined in Clause 22 are ignored by the devices specified in Clause 45.
The operation code field indicates the type of transaction being performed by the frame.
■
■
■
The port address (PRTAD). The port address is 5 bits, allowing 32 unique port addresses. The first port
address bit to be transmitted and received is the MSB of the address. A station management entity must have
a prior knowledge of the appropriate port address for each port to which it is attached, whether connected to
a single port or to multiple ports.
The device address is 5 bits, allowing 32 unique MDIO manageable devices (MMDs) per port. The first device
address bit transmitted and received is the MSB of the address.
The turnaround time is a 2-bit time spacing between the device address field and the data field of a
management frame to avoid contention during a read transaction. For a read or post-read-increment-address
transaction, both the station management entity (STA) and the MMD remain in a high-impedance state for the
first bit time of the turnaround. The MMD drives a 0 during the second bit time of the turnaround of a read or
postread-increment-address transaction. During a write or address transaction, the STA drives a 1 for the
first bit time of the turnaround and a 0 for the second bit time of the turnaround.
The address/data field is 16 bits. For an address cycle, it contains the address of the register to be accessed
on the next cycle. For the data cycle of a write frame, the field contains the data to be written to the register.
For a read or post-read-increment-address frame, the field contains the contents of the register. The first bit
transmitted and received is bit 15.
The idle condition on MDIO is a high-impedance state. All three state drivers are disabled and the MMDs
pullup resistor pulls the MDIO line to a one.
00 indicates that the frame payload contains the address of the register to access.
01 indicates that the frame payload contains data to be written to the register whose address was provided
in the previous address frame.
11 indicates that the frame is a read operation.
Table 3–55
3.6.10.3.MDIO Registers
The host processor can access the MDIO registers of a PHY device via an Avalon-MM
interface which are mapped in the address space. Each PHY device has 32 registers.
The IP core supports both Clause 22 and Clause 45, but electrical restrictions require
you to choose a single clause for your design.
For Clause 22, follow these steps:
1. Set up the mdio_addr0 register at address 0x03C, where:
2. Read or write to addresses 0x200 to 0x27C for direct access to the 32 register
■
■
addresses present (REGAD).
Bits 31:5 are unused
Bits 4:0 are PHYAD
describes the fields of the MDIO frame (Clause 45).
Description
10-Gbps Ethernet IP Functional Description
3–53