IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 47

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Table 3–9. Client Rx FIFO Interface (Part 2 of 2)
Figure 3–19. FIFO Client Rx Interface Timing
© July 2010 Altera Corporation
avl_st_rx_vlan_vlan_tag
avl_st_rx_vlan_vlan_tag
avl_st_rx_err
avl_st_rx_data[63:0]
avl_st_rx_vlan_tag
avl_st_rx_mty[2:0]
avl_st_rx_ena
avl_st_rx_eop
avl_st_rx_dav
avl_st_rx_sop
avl_st_rx_err
avl_st_rx_val
Signal Name
avl_st_clk
Figure 3–19
Dir
O
O
illustrates the timing for this interface.
Indicates the received frame is a stacked VLAN tagged frame.
Marks the current client packet as errored. This signal is asserted in conjunction
with avl_st_rx_eop.
one cycle from ena to val
Signals VLAN or stacked VLAN, if present
Description
10-Gbps Ethernet IP Functional Description
Signals error if present
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