IPR-10GETHERNET Altera, IPR-10GETHERNET Datasheet - Page 33

• Manufacturer Part Number: IPR-10GETHERNET
• Description: IP CORE Renewal Of IP-10GETHERNET
• Manufacturer: Altera

Specifications of IPR-10GETHERNET

• Software Application: IP CORE, Interface And Protocols, ETHERNET
• Supported Families: Quartus II
• Features: IEEE 802.3 2005 And 802.1Q Ethernet Standards, Management Data I/O (MDIO) Master Interface
• Core Architecture: FPGA
• Core Sub-architecture: Arria, HardCopy, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

MAC Functional Description
Table 3–1. FIFO Client Interface Signals–AnAvalon-ST Interface
© July 2010 Altera Corporation
avl_st_tx_dat[63:0]
avl_st_tx_ena
avl_st_tx_sop
avl_st_tx_eop
avl_st_tx_mty[2:0]
avl_st_tx_dav
avl_st_tx_err
Signal Name
Figure 3–6. Client–FIFO Interface, Tx Datapath
Table 3–1
Figure 3–7
optional FIFO.
Dir
O
I
I
I
I
I
I
describes the signals that comprise this interface.
shows the timing for the MAC/client interface when you include the
64-bit client (source) data.
When asserted, Indicates that avl_st_tx_dat, avl_st_tx_sop,
avl_st_tx_eop, and avl_st_tx_mty are valid.
Asserted for one cycle to indicate the start of client/source data.
Asserted for one cycle to indicate the end of client/source data.
Specifies how many bytes of avl_st_tx_dat[63:0] are empty when
avl_st_tx_eop is asserted as follows:
Value
0
1
2
3
4
5
6
7
Indicates that space is available in the FIFO and it is ready to consume client data.
This signal acts as the ready signal of the Avalon-ST interface. When this signal is
asserted, the client can continue to provide new data on the avl_st_tx_dat with
avl_st_tx_data_ena asserted. To backpressure to the client (source), the Tx
MAC deasserts the avl_st_tx_dav signal.
Marks the current client packet as errored. This signal must be asserted by the client
when it asserts the avl_st_tx_eop.
Client
Tx
Valid Data Bits
avl_tx_dat[63:0]
avl_tx_dat[63:8]
avl_tx_dat[63:16]
avl_tx_dat[63:24]
avl_tx_dat[63:32]
avl_tx_dat[63:40]
avl_tx_dat[63:48]
avl_tx_dat[63:56]
avl_tx_dat[63:0]
avl_st_tx_ena
avl_st_tx_sop
avl_st_tx_eop
avl_st_tx_err
avl_st_tx_mty[2:0]
avl_st_tx_dav
Description
10-Gbps Ethernet IP Functional Description
FIFO
Tx
3–7